DDR SDRAM 256Mb E-die (x4, x8)
Ball Description (Bottom
View)
DDR SDRAM
64M x 4bit
1
2
3
7
8
9
VSSQ
NC
VSS
A
VDD
NC
VDDQ
NC
VDDQ
DQ3
B
DQ0
VSSQ
NC
NC
VSSQ
NC
C
NC
VDDQ
NC
NC
VDDQ
DQ2
D
DQ1
VSSQ
NC
NC
VSSQ
DQS
E
NC
VDDQ
NC
VREF
VSS
DM
F
NC
VDD
NC
CK
CK
G
WE
CAS
A12
CKE
H
RAS
CS
A11
A9
J
BA1
BA0
A8
A7
K
A0
A10/AP
A6
A5
L
A2
A1
A4
VSS
M
VDD
A3
32M x 8bit
1
2
3
7
8
9
VSSQ
DQ7
VSS
A
VDD
DQ0
VDDQ
NC
VDDQ
DQ6
B
DQ1
VSSQ
NC
NC
VSSQ
DQ5
C
DQ2
VDDQ
NC
NC
VDDQ
DQ4
D
DQ3
VSSQ
NC
NC
VSSQ
DQS
E
NC
VDDQ
NC
VREF
VSS
DM
F
NC
VDD
NC
CK
CK
G
WE
CAS
A12
CKE
H
RAS
CS
A11
A9
J
BA1
BA0
A8
A7
K
A0
A10/AP
A6
A5
L
A2
A1
A4
VSS
M
VDD
A3
Organization
64Mx4
32Mx8
Row Address
A0~A12
A0~A12
Column Address
A0-A9, A11
A0-A9
DM is internally loaded to match DQ and DQS identically.
Row & Column address configuration
Rev. 1.1 September. 2003