DDR SDRAM 256Mb E-die (x4, x8)
AC Timing Parameters and Specifications
Parameter
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Internal write to read command delay
Clock cycle time
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
Write preamble setup time
Write preamble
Write postamble
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
Address and Control Input setup time
Address and Control Input hold time
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Mode register set cycle time
DQ & DM setup time to DQS, slew rate 0.5V/ns
DQ & DM hold time to DQS, slew rate 0.5V/ns
DQ & DM input pulse width
Control & Address input pulse width for each input
Refresh interval time
Output DQS valid window
Clock half period
Up to 128Mb
256Mb, 512Mb, 1Gb
CL=3.0
CL=2.5
Symbol
tRC
tRFC
tRAS
tRCD
tRP
tRRD
tWR
tWTR
tCK
tCH
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPRE
tWPST
tDSS
tDSH
tDQSH
tDQSL
tIS
tIH
tHZ
tLZ
tMRD
tDS
tDH
tDIPW
tIPW
tREFI
tQH
tHP
- CC(DDR400@CL=3)
Min
55
70
40
15
15
10
15
2
5
6
0.45
0.45
-0.55
-0.65
-
0.9
0.4
0.72
0
0.25
0.4
0.2
0.2
0.35
0.35
0.6
0.6
-
tAC min
2
0.4
0.4
1.75
2.2
15.6
7.8
tHP
-tQHS
min
tCH/tCL
-
-
tAC max
tAC max
0.6
10
12
0.55
0.55
+0.55
+0.65
0.4
1.1
0.6
1.28
70K
Max
DDR SDRAM
- C4(DDR400@CL=3)
Min
60
70
40
18
18
10
15
2
5
6
0.45
0.45
-0.55
-0.65
-
0.9
0.4
0.72
0
0.25
0.4
0.2
0.2
0.35
0.35
0.6
0.6
-
tAC min
2
0.4
0.4
1.75
2.2
15.6
7.8
tHP
-tQHS
min
tCH/tCL
-
-
tAC max
tAC max
0.6
10
12
0.55
0.55
+0.55
+0.65
0.4
1.1
0.6
1.28
70K
Max
Unit
ns
ns
ns
ns
ns
ns
ns
tCK
ns
ns
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ps
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
tCK
ns
ns
ns
ns
us
us
ns
ns
i, j
i, j
9
9
6
12
11, 12
h,7~10
h,7~10
3
3
4
5
13
16
Note
Rev. 1.1 September. 2003