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K4D263238A-GC50 Datasheet

  • K4D263238A-GC50

  • 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with ...

  • 17頁(yè)

  • SAMSUNG   SAMSUNG

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K4D263238A-GC
1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
FEATURES
鈥?2.5V + 5% power supply for device operation
鈥?2.5V + 5% power supply for I/O interface
鈥?SSTL_2 compatible inputs/outputs
鈥?4 banks operation
鈥?MRS cycle with address key programs
-. Read latency 3,4,5 (clock)
-. Burst length (2, 4, 8 and Full page)
-. Burst type (sequential & interleave)
鈥?Full page burst length for sequential burst type only
鈥?Start address of the full page burst should be even
鈥?All inputs except data & DM are sampled at the positive
going edge of the system clock
鈥?Differential clock input
鈥?No Wrtie-Interrupted by Read Function
鈥?4 DQS鈥檚 ( 1DQS / Byte )
128M DDR SDRAM
鈥?Data I/O transactions on both edges of Data strobe
鈥?DLL aligns DQ and DQS transitions with Clock transition
鈥?Edge aligned data & data strobe output
鈥?Center aligned data & data strobe input
鈥?DM for write masking only
鈥?Auto & Self refresh
鈥?32ms refresh period (4K cycle)
鈥?144-Ball FBGA
鈥?Maximum clock frequency up to 300MHz
鈥?Maximum data rate up to 600Mbps/pin
ORDERING INFORMATION
Part NO.
K4D263238A-GC33
K4D263238A-GC36
K4D263238A-GC40
K4D263238A-GC45
K4D263238A-GC50
Max Freq.
300MHz
275MHz
250MHz
222MHz
200MHz
Max Data Rate
600Mbps/pin
550Mbps/pin
500Mbps/pin
444Mbps/pin
400Mbps/pin
SSTL_2
(VDD/VDDQ=2.5V)
Interface
Package
144-Ball FBGA
GENERAL DESCRIPTION
FOR 1M x 32Bit x 4 Bank DDR SDRAM
The K4D263238A is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x1,048,576 words by
32 bits, fabricated with SAMSUNG
鈥?/div>
s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 2.4GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
- 3 -
Rev. 2.0 (Jan. 2003)

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