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K4D263238A-GC50 Datasheet

  • K4D263238A-GC50

  • 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with ...

  • 17頁(yè)

  • SAMSUNG   SAMSUNG

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K4D263238A-GC
AC OPERATING TEST CONDITIONS
(V
DD
=2.5V鹵5%, T
A
= 0 to 65擄C)
Parameter
Input reference voltage for CK(for single ended)
CK and CK signal maximum peak swing
CK signal minimum slew rate
Input Levels(V
IH
/V
IL
)
Input timing measurement reference level
Output timing measurement reference level
Output load condition
Value
0.50*V
DDQ
1.5
1.0
V
REF
+0.35/V
REF
-0.35
V
REF
V
tt
See Fig.1
V
tt
=0.5*V
DDQ
128M DDR SDRAM
Unit
V
V
V/ns
V
V
V
Note
R
T
=50鈩?/div>
Output
Z0=50鈩?/div>
V
REF
=0.5*V
DDQ
C
LOAD
=30pF
(Fig. 1) Output Load Circuit
CAPACITANCE
(V
DD
=2.5V, T
A
= 25擄C, f=1MHz)
Parameter
Input capacitance( CK, CK )
Input capacitance(A
0
~A
11
, BA
0
~BA
1
)
Input capacitance
( CKE, CS, RAS,CAS, WE )
Data & DQS input/output capacitance(DQ
0
~DQ
31
)
Input capacitance(DM0 ~ DM3)
Symbol
C
IN1
C
IN2
C
IN3
C
OUT
C
IN4
Min
1.0
1.0
1.0
1.0
1.0
Max
5.0
4.0
4.0
6.5
6.5
Unit
pF
pF
pF
pF
pF
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Parameter
Decoupling Capacitance between V
DD
and V
SS
Decoupling Capacitance between V
DDQ
and V
SSQ
Symbol
C
DC1
C
DC2
Value
0.1 + 0.01
0.1 + 0.01
Unit
uF
uF
Note :
1. V
DD
and V
DDQ
pins are separated each other.
All V
DD
pins are connected in chip. All V
DDQ
pins are connected in chip.
2. V
SS
and V
SSQ
pins are separated each other
All V
SS
pins are connected in chip. All V
SSQ
pins are connected in chip.
- 12 -
Rev. 2.0 (Jan. 2003)

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