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RV5C338A-E2 Datasheet

  • RV5C338A-E2

  • 3-WIRE SERIAL INTERFACE REAL-TIME CLOCK ICs WITH VOLTAGE MON...

  • 52頁

  • RICOH

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R
脳
5C338A
8.4 Interrupt Process
8.4-1 Periodic Interrupt
Set Periodic Interrupt
Cycle Selection Bits
*
1
*
1) This step is intended to select the level mode as a waveform mode for the
periodic interrupt function.
*
2) This step is intended to set the CTFG bit to 0 in the control register 2 to
cancel an interrupt to the CPU.
Generate Interrupt to CPU
CTFG=1?
YES
Periodic Interrupt Process
NO
Other Interrupt
Processes
Write 鈥溍?1,脳,1,脳,0,1,1鈥?/div>
to Control Register 2
*
2
8.4-2 Alarm Interrupt
WALE or DALE=0
Set Alarm Minute, Hour,
and Day-of-week Registers
WALE or DALE=1
*
1
*
1) This step is intended to once disable the alarm interrupt circuit by setting
the WALE and DALE bits to 0 in anticipation of the coincidental occurrence
of a match between current time and preset alarm time in the process of
setting the alarm interrupt function.
*
2) This step is intended to enable the alarm interrupt function after completion
*
2
of all alarm interrupt settings.
3) This step is intended to once cancel the alarm interrupt function by writing
*
the settings of 鈥溍?1,脳,1,脳,1,0,1鈥?and 鈥溍?1,脳,1,脳,1,1,0鈥?to the Alarm_W
registers and the Alarm_D registers, respectively.
Generate Interrupt to CPU
NO
WAFG or DAFG=1?
YES
Conduct Alarm Interrupt
Other Interrupt
Processes
Write 鈥溍?1,脳,1,脳,1,0,1鈥?/div>
to Control Register 2
*
3
46

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