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RV5C338A-E2 Datasheet

  • RV5C338A-E2

  • 3-WIRE SERIAL INTERFACE REAL-TIME CLOCK ICs WITH VOLTAGE MON...

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5C338A
8.3 Reading Time and Calendar Data
8.3-1 Ordinary Process of Reading Time and Calendar Data
*
1) This step of waiting is detailed in 鈥?.5 Considerations in Reading and
Writing Time Data鈥?
Wait for 31碌s
*
1
Read from Time Counter
and Calendar Counter
8.3-2 Basic Process of Reading Time and Calendar Data Synchronized with Periodic Interrupt
Set Periodic Interrupt
Cycle Selection Bits
*
1
*
1) This step is intended to select the level mode as a waveform mode for the
periodic interrupt function.
2) If this step is completed within 1 second, the step of waiting described in
*
鈥?.3-1 Ordinary Process of Reading Time and Calendar Data鈥?above need
not be conducted. This step is detailed in 鈥?.5 Considerations in Reading
and Writing Time Data鈥?
Generate Interrupt in CPU
CTFG=1?
YES
Read from Time Counter
and Calendar Counter
NO
*
3) This step is intended to set the CTFG bit to 0 in the control register 2 to
cancel an interrupt to the CPU.
*
2
*
3
Other Interrupt
Processes
Write 鈥溍?1,脳,1,脳,0,1,1鈥?/div>
to Control Register 2
44

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