R
脳
5C338A
6.4 Connection of CE Pin
Observe the following precautions when you connect the CE pin.
1) The CE pin is configured to enable the oscillation halt sensing circuit only when driven low. As such, it should be
driven low or open at power-on from 0 volts.
2) The CE pin should also be driven low or open immediately upon the host going down (see 鈥?.5 Considerations in
Reading and Writing Time Count Data鈥?.
3) The reading function should be disrupted when the CE signal goes to 鈥渓ow鈥?during read cycle. While, the upper 4
bits of the data might be written to the inner shift register when the CE signal goes to 鈥渓ow鈥?during write cycle.
(Because the writing function is executed 4 bits by 4 bits.) In either case, after the CE signal returns to 鈥淗igh鈥?
no trouble will occur in the next read or write cycle.
2
3
I/O
CONTROL
SCLK
SIO
V
DD
Lower limit operating voltage
for the CPU
Backup voltage
CE
4
CE
MIN. 0碌s
MIN. 0碌s
0.2脳V
DD
MIN. 0碌s
40