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RV5C338A-E2 Datasheet

  • RV5C338A-E2

  • 3-WIRE SERIAL INTERFACE REAL-TIME CLOCK ICs WITH VOLTAGE MON...

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3-WIRE SERIAL INTERFACE REAL-TIME CLOCK IC
S
WITH VOLTAGE MONITORING FUNCTION
R
脳
5C338A
OUTLINE
The R
脳
5C338A are CMOS real-time clock ICs connected to the CPU by three signal lines CE (Chip Enable), SCLK
(Serial Clock), and SIO (Serial Input/Output), and configured to perform serial transmission of time and calendar
data to the CPU. These models incorporate different functional circuits. The periodic interrupt circuit is configured
to generate interrupt signals with six selectable interrupts ranging from 0.5 seconds to 1 month. The 2 alarm
circuits generate interrupt signals at preset times. The oscillation circuit is driven under constant voltage so that
fluctuations in oscillation frequency due to voltage are small and supply current is also small (TYP. 0.35碌A(chǔ) at 3
volts). The oscillation halt sensing circuit can be used to judge the validity of internal data in such events as power-
on. The supply voltage monitoring circuit is configured to record a drop in supply voltage below two selectable
supply voltage monitoring threshold settings. The 32-kHz clock output function is intended to output sub-clock
pulses for the external microcomputer. The oscillation adjustment circuit is intended to adjust time counts with
high precision by correcting deviations in the oscillation frequency of the crystal oscillator. These models come in
an ultra-compact 10-pin SSOP (RS5C338A with a height of 1.25mm and a pin pitch of 0.5mm)and 10-pin SSOP-G
(RV5C338A with a height of 1.2mm and a pin pitch of 0.5mm).
FEATURES
鈥?Timekeeping supply voltage ranging from 1.45 to 5.5 volts
鈥?Low supply current: TYP. 0.35碌A(chǔ) (MAX. 0.8碌A(chǔ)) at 3 volts (at 25藲C)
鈥?Only three signal lines (SCLK, SIO, and CE) required for connection to the CPU.
Maximum clock frequency of 2 MHz (with V
DD
of 5 volts)
鈥?Time counters (counting hours, minutes, and seconds) and calendar counters (counting years, months, days, and
weeks) (in BCD format)
鈥?1900/2000 identification bit for Year 2000 compliance
鈥?Interrupt circuit configured to generate interrupt signals (with interrupts ranging from 0.5 seconds to 1 month) to
the CPU and provided with an interrupt flag and an interrupt halt circuit
鈥?2 alarm circuits (Alarm_W for week , hour , and minute alarm settings and Alarm_D for hour and minute alarm
settings)
鈥?32-kHz clock circuit (CMOS output, equipped with a control pin)
鈥?Oscillation halt sensing circuit which can be used to judge the validity of internal data
鈥?Supply voltage monitoring circuit with two supply voltage monitoring threshold settings
鈥?Automatic identification of leap years up to the year 2099
鈥?Selectable 12-hour and 24-hour mode settings
鈥?High precision oscillation adjustment circuit
鈥?Built-in oscillation stabilization capacitors (C
G
and C
D
)
鈥?CMOS process
鈥?Ultra-compact 10-pin SSOP (RS5C338A with a height of 1.25mm and size of 6.4
脳
3.5mm)
Ultra-compact 10-pin SSOP-G (RV5C338A with a height of 1.20mm and size of 4.0
脳
2.9mm)
1

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