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RV5C338A-E2 Datasheet

  • RV5C338A-E2

  • 3-WIRE SERIAL INTERFACE REAL-TIME CLOCK ICs WITH VOLTAGE MON...

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  • 52頁

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RS5C338A
2.5-3 Year Counter (at Address 6h)
D7
Y
80
Y
80
Indefinite
D6
Y
40
Y
40
Indefinite
D5
Y
20
Y
20
Indefinite
D4
Y
10
Y
10
Indefinite
D3
Y
8
Y
8
Indefinite
D2
Y
4
Y
4
Indefinite
D1
Y
2
Y
2
Indefinite
D0
Y
1
Y
1
Indefinite
(For writing)
(For reading)
Default settings*
*
)
Default settings: Default value means read/written values when the XSTP bit is set to 鈥?鈥?due to power-on from 0 volts or supply voltage drop.
2.6 Oscillation Adjustment Register (at Address 7h)
D7
(0)
(0)
0
D6
F
6
F
6
0
D5
F
5
F
5
0
D4
F
4
F
4
0
D3
F
3
F
3
0
D2
F
2
F
2
0
D1
F
1
F
1
0
D0
F
0
F
0
0
(For writing)
(For reading)
Default settings*
*
)
Default settings: Default value means read/written values when the XSTP bit is set to 鈥?鈥?due to power-on from 0 volts or supply voltage drop.
2.6-1 (0) Bit
The (0) bit should be set to 0 to allow writing to the oscillation adjustment register. The (0) bit will be set to 0 when
the XSTP bit is set to 1 in the control register 2.
2.6-2 F
6
to F
0
The oscillation adjustment circuit is configured to change time counts of 1 second on the basis of the settings of the
oscillation adjustment register when the second digits read 00, 20, or 40 seconds. Normally, the second counter is
incremented once per 32768 32.768-kHz clock pulses generated by the crystal oscillator. Writing to the F
6
to F
0
bits
activates the oscillation adjustment circuit.
路 The oscillation adjustment circuit will not operate with the same timing (00, 20, or 40 seconds) as the timing of
writing to the oscillation adjustment register.
路 The F
6
bit setting of 0 causes an increment of time counts by ((F
5
, F
4
, F
3
, F
2
, F
1
, F
0
) 鈥?)
2.
The F
6
bit setting of 1 causes a decrement of time counts by (( F
5
, F
4
, F
3
, F
2
, F
1
, F
0
) +1)
2.
The settings of 鈥?/div>
*
, 0, 0, 0, 0, 0,
*
鈥?( 鈥?/div>
*
鈥?representing either 鈥?鈥?or 鈥?鈥?) in the F
6
, F
5
, F
4
, F
3
, F
2
, F
1
, and F
0
bits
cause neither an increment nor decrement of time counts.
Example:
When the second digits read 00, 20, or 40, the settings of 鈥?, 0, 0, 0, 1, 1, 1鈥?in the F
6
, F
5
, F
4
, F
3
, F
2
, F
1
, and F
0
bits
cause an increment of the current time counts of 32768 by (7鈥?)
2 to 32780 (a current time count loss). When the
second digits read 00, 20, or 40, the settings of 鈥?, 0, 0, 0, 0, 0, 1鈥?in the F
6
, F
5
, F
4
, F
3
, F
2
, F
1
, and F
0
bits cause neither
an increment nor a decrement of the current time counts of 32768.
When the second digits read 00, 20, or 40, the settings of 鈥?, 1, 1, 1, 1, 1, 0鈥?in the F
6
, F
5
, F
4
, F
3
, F
2
, F
1
, and F
0
bits
cause a decrement of the current time counts of 32768 by (鈥?)
2 to 32764 (a current time count gain).
18

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