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RV5C338A-E2 Datasheet

  • RV5C338A-E2

  • 3-WIRE SERIAL INTERFACE REAL-TIME CLOCK ICs WITH VOLTAGE MON...

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  • RICOH

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R
脳
5C338A
2.1-3 CLEN2
32-kHz Clock Output Bit 2
CLEN2
Description
0
1
Enabling the 32-kHz clock circuit
Disabling the 32-kHz clock circuit
(Default setting)
For the R
脳
5C338A, setting the CLEN2 bit or the CLEN1 bit (D3 in the control register 2) to 0, and the CLKC pin to
high specifies generating clock pulses with the oscillation frequency of the 32.768-kHz crystal oscillator for output
from the 32KOUT pin. Conversely, setting both the CLEN1 and the CLEN2 bit to 1 or CLKC pin to low specifies
disabling (鈥淟鈥? such output.
2.1-4 TEST
Test Bit
TEST
Description
0
1
Normal operation mode
Test mode
(Default setting)
The TEST bit is used only for testing in the factory and should normally be set to 0.
2.1-5 CT
2
, CT
1
, and CT
0
Periodic Interrupt Selection Bits
Description
CT
2
CT
1
CT
0
Waveform mode
Interrupt cycle and falling timing
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
鈥?/div>
鈥?/div>
Pulse Mode
Pulse Mode
Level Mode
Level Mode
Level Mode
Level Mode
Off (鈥淗鈥?
Fixed at low (鈥淟鈥?
2Hz (Duty cycle of 50%)
1Hz (Duty cycle of 50%)
Once per 1 second (Synchronized with second counter increment)
Once per minute (at 00 seconds of every minute)
Once per hour (at 00 minutes and 00 seconds of every hour)
Once per month (at 00 hours, 00 minutes, and 00 seconds of first day of every month)
(Default setting)
1) Pulse Mode : 2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the second counter
as illustrated in the timing chart on the next page.
11

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