鈥?/div>
WALE DALE 12/24 CLEN2 TEST
VDSL VDET
SCRATCH
XSTP CLEN1 CTFG WAFG DAFG
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1) All the data listed above accept both reading and writing.
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2) The data marked with 鈥溾€撯€?is invalid for writing and reset to 0 for reading.
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3) When the XSTP bit is set to 1 in control register 2, all the bits are reset to 0 in oscillation adjustment register 1, control register 1 and control register 2
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excluding the XSTP bit.
4) Writing to the oscillation adjustment register requires zero filling the (0) bit.
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