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K4H1G0638C-UC/LB0 Datasheet

  • K4H1G0638C-UC/LB0

  • Stacked 1Gb C-die DDR SDRAM Specification

  • 23頁

  • SAMSUNG   SAMSUNG

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DDR SDRAM stacked 1Gb C-die (x4/x8)
1.0 Key Features
鈥?Double-data-rate architecture; two data transfers per clock cycle
鈥?Bidirectional data strobe
DQS
鈥?Four banks operation
鈥?Differential clock inputs(CK and CK)
鈥?DLL aligns DQ and DQS transition with CK transition
鈥?MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
鈥?All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
鈥?Data I/O transactions on both edges of data strobe
鈥?Edge aligned data output, center aligned data input
鈥?DM for write masking only (x4, x8)
鈥?Auto & Self refresh
鈥?7.8us refresh interval(8K/64ms refresh)
鈥?Maximum burst refresh cycle : 8
鈥?66pin TSOP II
Pb-Free
package
鈥?/div>
RoHS compliant
DDR SDRAM
2.0 Ordering Information
Part No.
K4H1G0638C-UC/LA2
K4H1G0638C-UC/LB0
K4H1G0738C-UC/LA2
K4H1G0738C-UC/LB0
Org.
st.256M x 4
st.128M x 8
Max Freq.
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
Interface
SSTL2
SSTL2
Package
66pin TSOP II
66pin TSOP II
3.0 Operating Frequencies
A2(DDR266@CL=2.0)
Speed @CL2
Speed @CL2.5
Speed @CL3
CL-tRCD-tRP
133MHz
133MHz
-
2-3-3
B0(DDR266@CL=2.5)
100MHz
133MHz
-
2.5-3-3
Rev. 1.1 June. 2005

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