鈥?/div>
+
Error Amp.2
7
C2
PMOS
EXT2
VFM2
6
L
+
C1
SBD
V
OUT2
R2
R1
CSW
V
DD
V
REF
The DC/DC2 can operate by an input voltage to the V
DD
pin. A change in the V
OUT2
will feed back to the internal error
amplifier through external voltage setting resistors. The V
REF
voltage should be provided from externally fixed power sup-
ply such as V
OUT1
.
When the feed back voltage to the Error Amp.2 is higher than the ground voltage, the error amplifier enables oscillation
otherwise, it will stop oscillation.
Pulses from the 鈥淥SC鈥?circuit have a duty cycle of 50% and it makes VFM operation allowable.
There might be certain cases that the duty cycles become smaller temporarily at light load current. The output of 鈥淓XT2鈥?/div>
is driven by CMOS buffer operated V
DD
and GND.
A PMOS driver will be connected to the 鈥淓XT2鈥?pin and its switching operation generates negative output voltage through
energy accumulated in an inductor.
The DC/DC1 can be shut down by CSW pin. When the CSW pin is High, V
DD
level, the DC/DC1 is enabled and when the
CSW pin is 鈥淟鈥? GND level, the DC/DC1 is disabled. The EXT2 pin outputs 鈥淗鈥?while the DC/DC2 is disabled.
鈥?Set Output Voltage DC/DC 2
V
OUT2
is described as follows:
V
REF
: R1=|鈥揤
OUT2
| : R2
|鈥揤
OUT2
|=V
REF
脳
R2/R1,
thus, any output voltage of DC/DC2 can be set by R1 and R2.
Certain temperature coefficient of V
OUT2
can be set by using R1, R2 having such temperature characteristics.
The FB2 voltage is controlled to 0V and V
REF
is provided externally
39
                         
                        
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