DDR SDRAM 256Mb E-die (x4, x8) Pb-Free
B3
(DDR333@CL=2.5))
Min
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
Control & Address input pulse width
DQ & DM input pulse width
Power down exit time
Exit self refresh to non-Read command
Exit self refresh to read command
Refresh interval time
Output DQS valid window
Clock half period
Data hold skew factor
DQS write postamble time
Active to Read with Auto precharge
command
Autoprecharge write recovery +
Precharge time
tMRD
tDS
tDH
tIPW
tDIPW
tPDEX
tXSNR
tXSRD
tREFI
tQH
tHP
tQHS
tWPST
tRAP
0.4
18
(tWR/tCK)
+
(tRP/tCK)
tHP
-tQHS
tCLmin
or tCHmin
12
0.45
0.45
2.2
1.75
6
75
200
7.8
-
-
0.55
0.6
0.4
20
(tWR/tCK)
+
(tRP/tCK)
tHP
-tQHS
tCLmin
or tCHmin
DDR SDRAM
B0
(DDR266@CL=2.5))
Min
15
0.5
0.5
2.2
1.75
7.5
75
200
7.8
-
-
0.75
0.6
0.4
20
(tWR/tCK)
+
(tRP/tCK)
tHP
-tQHS
tCLmin
or tCHmin
7.8
-
-
0.75
0.6
Parameter
Symbol
A2
(DDR266@CL=2.0)
Min
15
0.5
0.5
2.2
1.75
7.5
75
200
Unit
ns
ns
ns
ns
ns
ns
ns
tCK
us
ns
ns
ns
tCK
Note
Max
Max
Max
j, k
j, k
8
8
4
11
10, 11
11
2
tDAL
tCK
13
System Characteristics for DDR SDRAM
The following specification parameters are required in systems using DDR333, DDR266 & DDR200 devices to ensure
proper system performance. these characteristics are for system simulation purposes and are guaranteed by design.
Table 1 : Input Slew Rate for DQ, DQS, and DM
AC CHARACTERISTICS
PARAMETER
DQ/DM/DQS input slew rate measured between
VIH(DC), VIL(DC) and VIL(DC), VIH(DC)
SYMBOL
DCSLEW
DDR333
MIN
TBD
MAX
TBD
DDR266
MIN
TBD
MAX
TBD
DDR200
MIN
0.5
MAX
4.0
Units
V/ns
Notes
a, m
Table 2 : Input Setup & Hold Time Derating for Slew Rate
Input Slew Rate
0.5 V/ns
0.4 V/ns
0.3 V/ns
tIS
0
+50
+100
tIH
0
0
0
Units
ps
ps
ps
Notes
i
i
i
Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate
Input Slew Rate
0.5 V/ns
0.4 V/ns
0.3 V/ns
tDS
0
+75
+150
tDH
0
+75
+150
Units
ps
ps
ps
Notes
k
k
k
Rev. 1.1 October, 2004