RV5VE0
脳脳脳
5) Output Delay Time (falling edge) vs.
Load Capacitance
Topt = 25藲C
Detector 2
without C
D
Detector 1,2
V
DD
= 3.0V
Output Delay Time t
PLH
(s)
6) Output Delay Time (rising edge) vs.
Input Voltage
Topt = 25藲C
without C
OUT
Detector 1,2
and C
D
10
-3
Output Delay Time t
PHL
(s)
10
-3
10
-4
Detector 2
10
-4
10
-5
Detector 2
Detector 1
Detector 1
10
-6
10
-9
10
-8
10
-7
Load Capacitance C
OUT
(F)
10
-6
10
-5
0
2
4
6
8
10
Input Voltage V
DD
(V)
7) Output Delay Time (falling edge) vs.
C
D
Pin External Capacitance
Detector 2
10
Output Delay Time t
PHL
(s)
-5
8) Output Delay Time (rising edge) vs.
C
D
Pin External Capacitance
10
- 0
Output Delay Time t
PLH
(s)
Topt = 25藲C
without C
D
Detector 2
Topt = 25藲C
10
- 1
10
- 2
10
-6 -9
10
10
-7
10
-8
10
-6
C
D
Pin External Capacitance C
D
(F)
10
- 3 - 9
10
10
- 8
10
- 7
10
- 6
C
D
Pin External Capacitance C
D
(F)
45