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K4E640412E-TI50 Datasheet

  • K4E640412E-TI50

  • 16M x 4bit CMOS Dynamic RAM with Extended Data Out

  • 21頁

  • SAMSUNG   SAMSUNG

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Industrial Temperature
K4E660412E,K4E640412E
NOTES
1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
2. Input voltage levels are Vih/Vil. V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals. Transition
times are measured between V
IH
(min) and V
IL
(max) and are assumed to be 2ns for all inputs.
3. Measured with a load equivalent to 1 TTL load and 100pF.
4. Operation within the
t
RCD
(max) limit insures that
t
RAC
(max) can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then access time is controlled exclusively by
t
CAC
.
5. Assumes that
t
R C D
鈮?/div>
t
R C D
(max).
6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V
oh
or V
ol
.
7.
t
W C S
,
t
RWD
,
t
CWD
and
t
AWD
are non restrictive operating parameters. They are included in the data sheet as electric charac-
teristics only. If
t
WCS
鈮?/div>
t
W C S
(min), the cycles is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If
t
C W D
鈮?/div>
t
C W D
(min),
t
RWD
鈮?/div>
t
RWD
(min) and
t
AWD
鈮?/div>
t
AWD
(min), then the cycle is a read-modify-write cycle
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the
condition of the data out is indeterminate.
8. Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
9. This parameters are referenced to the CAS falling edge in early write cycles and to the W falling edge in OE controlled write
cycle and read-modify-write cycles.
10. Operation within the
t
RAD
(max) limit insures that
t
RAC
(max) can be met.
t
RAD
(max) is specified as a reference point only.
If
t
RAD
is greater than the specified
t
RAD
(max) limit, then access time is controlled by
t
AA
.
11. These specifications are applied in the test mode.
12. In test mode read cycle, the value of
t
RAC
,
t
AA
,
t
CAC
is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
13. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going.
If CAS goes high before RAS high going, the open circuit condition of the output is achieved by RAS high going.
14.
t
ASC
鈮?ns,
Assume t
T
= 2.0ns, if t
ASC
鈮?ns,
then t
HPC
(min) and t
CAS
(min) must be increased by the value of "6ns-t
ASC
".
15. If
t
R A S S
鈮?00us,
then RAS precharge time must use
t
RPS
instead of
t
R P
.
16. For RAS-only-Refresh and Burst CAS-before-RAS refresh mode, 4096 cycles(4K/8K) of burst refresh must be executed
within 64ms before and after self refresh, in order to meet refresh specification.
17. For distributed CAS -before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before
and after self refresh in order to meet refresh specification.
CMOS DRAM

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