K3S7V2000M-TC
Synch. MROM
Read Cycle III : Clock Suspend @RAS Latency = 2, CAS Latency=5, Burst Length=4
t
CH
4
0
CLK
1
2
3
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
t
CC
CKE
t
CL
*Note 1
Internal
CLK
CS
RAS
Latency
t
SH
RAS
t
SS
CAS
t
SH
ADDR
RAa
t
SS
t
VCVC
= 4 clocks at BL=4
*Note 2
CAa
Data
Burst Length=4
Qa0
Qa1
Qa2 Qa3
MR
Row Active
Read
Clock Suspend Resume
:
Don't Care
Note :
1. From next clock after CKE goes low, clock suspension begins.
2. For clock suspension, data output state is held & maintained.