K4C89183AF
Multiple Bank Write Timing (CL=6)
0
CLK
CLK
l
RBD
=2cycles
Command
WRA
LAL
WRA
LAL
DESL
WRA
l
RBD
=2cycles
LAL
WRA
l
RBD
=2cycles
LAL
WRA
l
RBD
=2cycles
LAL
WRA
l
RBD
=2cycles
LAL
WRA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Address
UA
Bank
"a"
LA
UA
Bank
"b"
LA
UA
Bank
"a"
LA
UA
Bank
"b"
LA
UA
Bank
"c"
LA
UA
Bank
"d"
LA
UA
Bank
"a"
Bank Add.
l
RC
(Bank"a")=7cycles
Unidirectional DS/QS mode
DS
(input)
QS
(Output)
Low
WL=5
WL=5
DQ
(input)
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Da0 Da1 Da2 Da3 Db0 Db1
l
RC
(Bank"a")=7cycles
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(Output)
WL=5
DQ
(input)
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Da0 Da1 Da2 Da3 Db0 Db1
WL=5
Note :I
RC
to the same bank must be satisfied.
- 39 -
REV. 0.7 Jan. 2005