K4C89183AF
Multiple Bank Write Timing (CL=4)
0
CLK
CLK
l
RBD
=2cycles
Command
WRA
LAL
WRA
LAL
DESL
WRA
l
RBD
=2cycles
LAL
WRA
l
RBD
=2cycles
LAL
WRA
l
RBD
=2cycles
LAL
WRA
l
RBD
=2cycles
LAL
WRA
LAL
WRA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Address
UA
Bank
"a"
LA
UA
Bank
"b"
LA
UA
Bank
"a"
LA
UA
Bank
"b"
LA
UA
Bank
"c"
LA
UA
Bank
"d"
LA
UA
Bank
"a"
LA
UA
Bank
"b"
Bank Add.
l
RC
(Bank"a")=5cycles
Unidirectional DS/QS mode
l
RC
(Bank"b")=5cycles
DS
(input)
QS
(Output)
Low
WL=3
WL=3
DQ
(Input)
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Dc0 Dc1 Dc2 Dc3 Dd0 Dd1
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(Output)
WL=3
DQ
(Input)
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Dc0 Dc1 Dc2 Dc3 Dd0 Dd1
WL=3
Note : l
RC
to the same bank must be satisfied
- 37 -
REV. 0.7 Jan. 2005