K4C89183AF
Multiple Bank Read Timing (CL=5)
0
CLK
CLK
l
RBD
=2cycles
Command
RDA
LAL
RDA
LAL
DESL
RDA
l
RBD
=2cycles
LAL
RDA
l
RBD
=2cycles
LAL
RDA
l
RBD
=2cycles
LAL
RDA
l
RBD
=2cycles
LAL
RDA
LAL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Address
UA
Bank
"a"
LA
UA
Bank
"b"
LA
UA
Bank
"a"
LA
UA
Bank
"b"
LA
UA
Bank
"c"
LA
UA
Bank
"d"
LA
UA
Bank
"a"
LA
Bank Add.
l
RC
(Bank"a")=6cycles
Unidirectional DS/QS mode
l
RC
(Bank"6")=6cycles
DS
(input)
QS
(Output)
Low
CL=5
CL=5
DQ
(Output)
Hi-Z
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(Output)
CL=5
DQ
(Output)
Hi-Z
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2
CL=5
Note : l
RC
to the same bank must be satisfied
- 35 -
REV. 0.7 Jan. 2005