K4C5608/1638C
AC Characteristics and Operating Conditions
(Notes : 1, 2)
Symbol
t
RC
t
CK
t
RAC
t
CH
t
CL
t
CKQS
t
QSQ
t
AC
t
OH
t
QSPRE
t
HP
t
QSP
t
QSQV
t
DQSS
t
DSPRE
Random Cycle Time
CL = 3
Clock Cycle Time
CL = 4
Random Access Time
Clock High Time
Clock Low Time
DQS Access Time from CLK
Data Output Skew from DQS
Data Access Time from CLK
Data Output Hold Time from CLK
DQS(Read) Preamble Pulse Width
CLK half period ( minium of Actual t
CH
, t
CL
)
DQS(Read) Pulse Width
Data Output Valid Time from DQS
DQS(Write) Low to High Setup Time
DQS(Write) Preamble Pulse Width
5
-
0.45*t
CK
0.45*t
CK
-0.65
-
-0.65
-0.65
0.9*t
CK
-0.2
min(t
CH
, t
CL
)
7.5
22
-
-
0.65
0.4
0.65
0.65
1.1*t
CK
+0.2
-
-
-
1.25*t
CK
-
-
-
0.55*t
CK
-
-
-
-
-
0.5*t
CK
-
-
-
-
-
-
-
0.65
-
0.65
-
-
1
5
5.5
-
0.45*t
CK
0.45*t
CK
-0.75
-
-0.75
-0.75
256Mb Network-DRAM
D4(400Mbps)
Min
25
5.5
Item
DA(366Mbps)
Min
27.5
6
D3(333Mbps)
Min
30
6.5
6
-
0.45*t
CK
0.45*t
CK
-0.85
-
-0.85
-0.85
0.9*t
CK
-0.2
min(t
CH
, t
CL
)
Max
-
7.5
Max
-
7.5
7.5
24
-
-
0.75
0.45
0.75
0.75
1.1*t
CK
+0.2
-
-
Max
-
7.5
7.5
26
-
-
0.85
0.5
0.85
0.85
1.1*t
CK
+0.2
-
-
-
1.25*t
CK
-
-
-
0.55*t
CK
-
-
-
-
-
0.5*t
CK
-
-
-
-
-
-
-
0.85
-
0.85
-
-
1
5
Units Notes
3
3
3
3
3
3
3, 8
4
3, 8
3, 8
3
0.9*t
CK
-0.2
min(t
CH
, t
CL
)
t
HP
-0.55
t
HP
-0.55
0.75*t
CK
0.4*t
CK
0
0.25*t
CK
0.45*t
CK
CL = 3
1.3
1.3
0.45*t
CK
CL = 3
CL = 4
1.3
1.3
-0.5*t
CK
0.5
0.5
1.5
0.9
0.9
2.0
-0.65
-
-0.65
-0.65
0
2
0.1
-0.5*t
CK
t
HP
-0.6
t
HP
-0.6
0.75*t
CK
0.4*t
CK
0
0.25*t
CK
0.45*t
CK
1.4
1.4
0.45*t
CK
1.4
1.4
-0.5*t
CK
0.5
0.5
1.5
0.9
0.9
2.0
-0.75
-
-0.75
-0.75
0
2
0.1
-0.5*t
CK
t
HP
-0.65
t
HP
-0.65
4
4
3
4
3
3
4
ns
3, 4
3, 4
4
3, 4
3, 4
1.25*t
CK
-
-
-
0.55*t
CK
-
-
0.75*t
CK
0.4*t
CK
0
0.25*t
CK
0.45*t
CK
1.5
1.5
0.45*t
CK
t
DSPRES
DQS First Input Setup Time
t
DSPREH
DQS First Low Input Hold Time
t
DSP
t
DSS
t
DSPST
DQS High or Low Input Pulse Width
DQS Input Falling Edge to Clock Setup Time
CL = 4
DQS(Write) Postamble Pulse Width
t
DSPSTH
DQS(Write) Postamble Hold Time
t
DSSK
t
DS
t
DH
t
DIPW
t
IS
t
IH
t
IPW
t
LZ
t
HZ
t
QSLZ
t
QSHZ
t
QPDH
t
PDEX
t
T
t
FPDL
UDQS - LDQS Skew (x16)
Data Input Setup Time from DQS
Data Input Hold Time from DQS
Data Input pulse Width (for each device)
Command / Address Input Setup Time
Command / Address Input Hold Time
-
-
0.5*t
CK
-
-
-
-
-
-
-
0.75
-
0.75
-
-
1
5
1.5
1.5
-0.5*t
CK
0.6
0.6
1.9
1
1
2.2
-0.85
-
-0.85
-0.85
0
2
0.1
-0.5*t
CK
4
4
3
3
Command / Address Input Pulse Width (for each device)
Data-out Low Impedance Time from CLK
Data-out High Impedance Time from CLK
DQS-out Low Impedance Time from CLK
DQS-out High Impedance Time from CLK
Last Output to PD High Hold Time
Power Down Exit Time
Input Transition Time
PD Low Input Window for Self-Refresh Entry
3, 6, 8
3, 7, 8
3, 6, 8
3, 7, 8
3
3
- 11 -
REV. 0.7 Aug. 2003