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K4D553238F-JC50 Datasheet

  • K4D553238F-JC50

  • 256Mbit GDDR SDRAM

  • 298.88KB

  • 17頁(yè)

  • SAMSUNG   SAMSUNG

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K4D553238F-JC
FUNCTIONAL DESCRIPTION
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Power-Up Sequence
256M GDDR SDRAM
GDDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and keep CKE at low state (All other inputs may be undefined)
- Apply VDD before VDDQ .
- Apply VDDQ before VREF & VTT
2. Start clock and maintain stable condition for minimum 200us.
3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high .
4. Issue precharge command for all banks of the device.
5. Issue a EMRS command to enable DLL
6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.
7. Issue precharge command for all banks of the device.
8. Issue at least 2 or more auto-refresh commands.
9. Issue a mode register set command with A8 to low to initialize the mode register.
*1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6&7 is regardless of the order.
*1
*
1,2
Power up & Initialization Sequence
0
CK,CK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
~
~
~ ~
~
Command
precharge
ALL Banks
EMRS
MRS
DLL Reset
precharge
ALL Banks
1st Auto
Refresh
2nd Auto
Refresh
~ ~
~
t
RP
2 Clock min.
2 Clock min.
tRP
t
RFC
t
RFC
~
2 Clock min.
Mode
Register Set
Any
Command
~
Inputs must be
stable for 200us
* When the operating frequency is changed, DLL reset should be required again.
After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL.
~
~
200 Clock min.
- 7 -
Rev 1.0 (Mar. 2004)

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