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K4D551638D-TC60 Datasheet

  • K4D551638D-TC60

  • 256Mbit GDDR SDRAM

  • 18頁

  • SAMSUNG   SAMSUNG

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K4D551638D-TC
AC CHARACTERISTICS
Parameter
CK cycle time
CL=3
CL=4
Min
-
tCK
2.86
tCH
0.45
tCL
0.45
tDQSCK
-0.6
tAC
-0.6
tDQSQ
-
tRPRE
0.9
tRPST
0.4
tDQSS
0.85
tWPRES
0
tWPREH
0.35
tWPST
0.4
tDQSH
0.4
tDQSL
0.4
tIS
0.9
tIH
0.9
tDS
0.35
tDH
0.35
tCLmin
tHP
or
tCHmin
tHP-
tQH
0.35
Symbol
-2A
Max
10
0.55
0.55
0.6
0.6
0.35
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
-
-
-33
Min
-
3.3
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.35
0.35
tCLmin
or
tCHmin
tHP-
0.35
Max
10
0.55
0.55
0.6
0.6
0.35
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
-
-
-36
Min
-
3.6
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.4
0.4
tCLmin
or
tCHmin
tHP-
0.4
Max
10
0.55
0.55
0.6
0.6
0.4
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
-
-
256M GDDR SDRAM
-40
Min
-
4.0
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.4
0.4
tCLmin
or
tCHmin
tHP-
0.4
Max
10
0.55
0.55
0.6
0.6
0.4
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
-
-
-45
Min
4.5
-
0.45
0.45
-0.7
-0.7
-
0.9
0.4
0.8
0
0.3
0.4
0.45
0.45
1.0
1.0
0.45
0.45
tCLmin
or
tCHmin
tHP-
0.45
Max
10
0.55
0.55
0.7
0.7
0.45
1.1
0.6
1.2
-
-
0.6
0.55
0.55
-
-
-
-
-
-
Unit
ns
ns
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
Note
CK high level width
CK low level width
DQS out access time from CK
Output access time from CK
Data strobe edge to Dout edge
Read preamble
Read postamble
CK to valid DQS-in
DQS-In setup time
DQS-in hold time
DQS write postamble
DQS-In high level width
DQS-In low level width
Address and Control input setup
Address and Control input hold
DQ and DM setup time to DQS
DQ and DM hold time to DQS
Clock half period
Data output hold time from DQS
1
1
1
AC CHARACTERISTICS (I)
Parameter
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay for Read
RAS to CAS delay for Write
Row precharge time
Row active to Row active
Last data in to Row precharge
@Normal Precharge
Last data in to Row precharge
@Auto Precharge
Last data in to Read command
Col. address to Col. address
Mode register set cycle time
Auto precharge write recovery +
Precharge
Exit self refresh to read command
Power down exit time
Refresh interval time
Symbol
tRC
tRFC
tRAS
tRCDRD
tRCDW
tRP
tRRD
tWR
tWR_A
tCDLR
tCCD
tMRD
tDAL
tXSR
tPDEX
tREF
-2A
Min
15
17
10
5
3
5
3
3
3
3
1
2
8
200
3tCK
+tIS
7.8
Max
-
-
100K
-
-
-
-
-
-
-
-
-
-
-
-
-
Min
15
17
10
5
3
5
3
3
3
3
1
2
8
200
3tCK
+tIS
7.8
-33
Max
-
-
100K
-
-
-
-
-
-
-
-
-
-
-
-
-
Min
15
17
10
5
3
5
3
3
3
2
1
2
8
200
3tCK
+tIS
7.8
-36
Max
-
-
100K
-
-
-
-
-
-
-
-
-
-
-
-
-
Min
13
15
9
4
2
4
3
3
3
2
1
2
7
200
3tCK
+tIS
7.8
-40
Max
-
-
100K
-
-
-
-
-
-
-
-
-
-
-
-
-
Min
12
14
8
4
2
4
3
3
3
2
1
2
7
200
3tCK
+tIS
7.8
-45
Max
-
-
100K
-
-
-
-
-
-
-
-
-
-
-
-
-
Unit
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
us
1
1
1
Note
Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM
- 13 -
Rev 1.8 (Oct. 2003)

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