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TZA3004 Datasheet

  • TZA3004

  • SDH/SONET STM1/OC3 and STM4/OC12 transceiver

  • 28頁

  • PHILIPS

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Philips Semiconductors
Product speci鏗乧ation
SDH/SONET STM1/OC3 and STM4/OC12
transceiver
Transceiver pin descriptions
T
RANSMITTER INPUT SIGNALS
TZA3005H
Signal detect PECL (SDPECL)
This is a single-ended PECL input with an internal
pull-down resistor. This input is driven by an external
optical receiver module to indicate a loss of received
optical power (LOS). SDPECL is active HIGH when
SDTTL is at logic 0 and active LOW when SDTTL is at
logic 1or unconnected. When there is a loss of signal,
SDPECL is inactive and the bit-serial data on pins RXSD
and RXSDQ is internally forced to a constant zero. When
SDPECL is active, the bit-serial data on pins RXSD and
RXSDQ is processed normally (see Table 5).
Parallel data inputs (TXPD0 to TXPD7)
These are TTL data word inputs. The input data is aligned
with the TXPCLK parallel input clock. TXPD7 is the most
significant bit (corresponding to bit 1 of each PCM word,
the first bit transmitted). TXPD0 is the least significant bit
(corresponding to bit 8 of each PCM word, the last bit
transmitted). Bits TXPD0 to TXPD7 are sampled on the
rising edge of TXPCLK. If a 4-bit bus width is selected,
TXPD7 is the most significant bit and TXPD4 is the least
significant bit. Inputs TXPD0 to TXPD3 are unused.
Signal detect TTL (SDTTL)
This is a single-ended TTL input with an internal pull-up
resistor. This input is driven by an external optical receiver
module to indicate a loss of received optical power (LOS).
SDTTL is active HIGH when pin SDPECL is logic 0 or
unconnected, and active LOW when pin SDPECL is at
logic 1. When there is a loss of signal, SDTTL is inactive
and the bit-serial data on pins RXSD and RXSDQ is
internally forced to a constant zero. When SDTTL is active,
the bit-serial data on pins RXSD and RXSDQ is processed
normally (see Table 5).
If pin SDTTL instead of pin SDPECL is to be connected to
the optical receiver module, connect pin SDPECL to a
logic HIGH-level to implement an active-LOW signal
detect, or leave pin SDPECL unconnected to implement
an active-HIGH signal detect.
Table 5
SDPECL/SDTTL truth table
SDTTL
0
1 or 鏗俹ating
0
1 or 鏗俹ating
RXPD OUTPUT DATA
0
RXSD input data
RXSD input data
0
Parallel clock input (TXPCLK)
This is a TTL input clock signal having a frequency of
either 19.44, 38.88, 77.76 or 155.52 MHz and a duty factor
of nominally 50%, to which input data bits TXPD0 to
TXPD7 are aligned. TXPCLK transfers the input data to a
holding register in the parallel-to-serial converter.
The rising edge of TXPCLK samples bits TXPD0 to
TXPD7. After a master reset, one rising edge of TXPCLK
is required to fully initialize the internal data path.
R
ECEIVER INPUT SIGNALS
Receive serial data (RXSD and RXSDQ)
These are differential PECL serial data inputs, normally
connected to an optical receiver module or to the TZA3004
data and clock recovery unit, and clocked by RXSCLK and
RXSCLKQ. These inputs can be AC coupled without
external biasing.
SDPECL
0 or 鏗俹ating
0 or 鏗俹ating
1
1
Receive serial clock (RXSCLK and RXSCLKQ)
These are differential PECL recovered clock signals
synchronized to the input data RXSD and RXSDQ. It is
used by the receiver as the master clock for framing and
deserialization functions. These inputs can be AC coupled
without external biasing.
C
OMMON INPUT SIGNALS
Out-of-frame (OOF)
This is a TTL signal which enables frame pattern detection
logic in the TZA3005H. The frame pattern detection logic
is enabled by a rising edge on pin OOF, and remains
enabled until a frame boundary is detected and OOF goes
LOW. OOF is an asynchronous signal with a minimum
pulse width of one RXPCLK period (see Fig.3).
Bus width selection (BUSWIDTH)
This is a TTL signal which selects 4-bit or 8-bit operation
for the transmit and receive parallel interfaces.
BUSWIDTH LOW selects a 4-bit bus width. BUSWIDTH
HIGH selects an 8-bit bus width.
2000 Feb 17
9

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