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TZA3004 Datasheet

  • TZA3004

  • SDH/SONET STM1/OC3 and STM4/OC12 transceiver

  • 28頁(yè)

  • PHILIPS

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Philips Semiconductors
Product speci鏗乧ation
SDH/SONET STM1/OC3 and STM4/OC12
transceiver
FEATURES
鈥?/div>
Supports STM1/OC3 (155.52 Mbits/s) and STM4/OC12
(622.08 Mbits/s)
鈥?/div>
Supports reference clock frequencies of 19.44, 38.88,
51.84 and 77.76 MHz
鈥?/div>
Meets Bellcore, ANSI and ITU-T specifications
鈥?/div>
Meets ITU jitter specification typically to a factor of 2.5
鈥?/div>
Integral high-frequency PLL for clock generation
鈥?/div>
Interface to TTL logic
鈥?/div>
Low jitter PECL (Positive Emitter Coupled Logic)
interface
鈥?/div>
4 or 8-bit STM1/OC3 TTL data path
鈥?/div>
4 or 8-bit STM4/OC12 TTL data path
鈥?/div>
No external filter components required
鈥?/div>
QFP64 package
鈥?/div>
Diagnostic and line loopback modes
鈥?/div>
Lock detect
鈥?/div>
LOS (Loss of Signal) input
鈥?/div>
Low power (0.9 W typical)
鈥?/div>
Selectable frame detection and byte realignment
鈥?/div>
Loop timing
鈥?/div>
Forward and reverse clocking
鈥?/div>
Squelched clock operation
鈥?/div>
Self-biased PECL inputs to support AC coupling.
APPLICATIONS
鈥?/div>
SDH/SONET modules
鈥?/div>
SDH/SONET-based transmission systems
鈥?/div>
SDH/SONET test equipment
鈥?/div>
ATM (Asynchronous Transfer Mode) over SDH/SONET
鈥?/div>
Add drop multiplexers
鈥?/div>
Broadband cross-connects
鈥?/div>
Section repeaters
鈥?/div>
Fibre optic test equipment
鈥?/div>
Fibre optic terminators.
ORDERING INFORMATION
TYPE
NUMBER
TZA3005H
PACKAGE
NAME
QFP64
DESCRIPTION
plastic quad 鏗俛t package; 64 leads (lead length 1.6 mm);
body 14
脳
14
脳
2.7 mm
GENERAL DESCRIPTION
TZA3005H
The TZA3005H SDH/SONET transceiver chip is a fully
integrated serialization/deserialization STM1/OC3
(155.52 Mbits/s) and STM4/OC12 (622.08 Mbits/s)
interface device. It performs all necessary serial-to-parallel
and parallel-to-serial functions in accordance with
SDH/SONET transmission standards. It is suitable for
SONET-based applications and can be used in
conjunction with the data and clock recovery unit
(TZA3004), optical front-end (TZA3023 with TZA3034/44)
and a laser driver (TZA3001). A typical network application
is shown in Fig.10.
A high-frequency phase-locked loop is used for on-chip
clock synthesis, which allows a slower external transmit
reference clock to be used. A reference clock of 19.44,
38.88, 51.84 or 77.76 MHz can be used to support existing
system clocking schemes. The TZA3005H also performs
SDH/SONET frame detection.
The low jitter PECL interface ensures that Bellcore, ANSI,
and ITU-T bit-error rate requirements are satisfied.
The TZA3005H is supplied in a compact QFP64 package.
VERSION
SOT393-1
2000 Feb 17
2

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