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TZA3004 Datasheet

  • TZA3004

  • SDH/SONET STM1/OC3 and STM4/OC12 transceiver

  • 130.78KB

  • 28頁

  • PHILIPS

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Philips Semiconductors
Product speci鏗乧ation
SDH/SONET STM1/OC3 and STM4/OC12
transceiver
TZA3005H
AC CHARACTERISTICS
For typical values, T
amb
= 25
擄C
and V
CC
= 3.3 V; minimum and maximum values are valid over entire T
j
and V
CC
ranges.
SYMBOL
General
f
TXSCLK(nom)
nominal TXSCLK frequency
f
REFCLK
as Table 2;
MODE = 0
MODE = 1
J
o
f
REFCLK(tol)
data output jitter
in lock; note 1
frequency tolerance of REFCLK meets SONET output
frequency speci鏗乧ation;
note 1
rise/fall time PECL outputs
20% to 80%; 50
鈩?/div>
load
to V
CC
鈭?/div>
2.0 V
155.517
622.068
鈭?/div>
鈭?0
155.52
622.08
0.004
鈭?/div>
155.523
622.092
0.006
+20
MHz
MHz
UI (RMS)
ppm
PARAMETER
CONDITION
MIN.
TYP.
MAX.
UNIT
t
r
, t
f
鈭?/div>
220
450
ps
Receiver timing
(see Figs 6 and 7)
C
L
未
RXPCLK
t
PD
t
su
t
h
TTL output load capacitance
duty factor of RXPCLK
propagation delay; RXPCLK
LOW to RXPDn, FP
set-up time; RXSD/RXSDQ to
RXSCLK/RXSCLKQ
hold time; RXSD/RXSDQ to
RXSCLK/RXSCLKQ
note 2
鈭?/div>
40
鈭?.5
400
400
鈭?/div>
50
+1.5
鈭?/div>
鈭?/div>
15
60
+2.5
鈭?/div>
鈭?/div>
pF
%
ns
ps
ps
Transmitter timing
(see Figs 8 and 9)
未
TXSCLK
t
su
t
h
t
PD
Notes
1. Jitter on pins REFCLK/REFCLKQ complies with Table 3.
2. Minimum value is 35% in STM4 nibble mode.
duty factor of TXSCLK
set-up time; TXPDn to TXPCLK
hold time; TXPDn to TXPCLK
propagation delay time;
TXSCLK LOW to TXSD
40
鈭?.5
1.5
鈭?/div>
50
鈭?/div>
鈭?/div>
鈭?/div>
60
鈭?/div>
鈭?/div>
440
%
ns
ns
ps
2000 Feb 17
16

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