DDR SDRAM 128Mb F-die (x4, x8)
AC Timming Parameters & Specifications
Parameter
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Col. address to Col. address delay
Clock cycle time
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
DQS-in cycle time
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup time(slow)
Address and Control Input hold time(slow)
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
Control & Address input pulse width
DQ & DM input pulse width
Power down exit time
Exit self refresh to non-Read command
Exit self refresh to read command
Refresh interval time
Output Slew Rate Matching Ratio(rise to fall)
CL=2.0
CL=2.5
DDR SDRAM
Symbol
tRC
tRFC
tRAS
tRCD
tRP
tRRD
tWR
tWTR
tCCD
tCK
tCH
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPRE
tDSS
tDSH
tDQSH
tDQSL
tDSC
tIS
tIH
tIS
tIH
tHZ
tLZ
tMRD
tDS
tDH
tIPW
tDIPW
tPDEX
tXSNR
tXSRD
tREFI
tSLMR
B3
A2
B0
A0
(DDR333@CL=2.5 (DDR266@CL=2.0 (DDR266@CL=2.5 (DDR200@CL=2.0
Min
60
72
42
18
18
12
15
1
1
7.5
6
0.45
0.45
-0.6
-0.7
-
0.9
0.4
0.75
0
0.25
0.2
0.2
0.35
0.35
0.9
0.75
0.75
0.8
0.8
+0.7
-0.7
12
0.45
0.45
2.2
1.75
6
75
200
7.8
0.67
1.5
0.67
+0.7
-0.75
15
0.5
0.5
2.2
1.75
7.5
75
200
7.8
1.5
0.67
1.1
12
12
0.55
0.55
+0.6
+0.7
0.45
1.1
0.6
1.25
70K
Unit
ns
ns
Note
Max
Min
65
75
45
20
20
15
15
1
1
7.5
7.5
0.45
0.45
-0.75
-0.75
-
0.9
0.4
0.75
0
0.25
0.2
0.2
0.35
0.35
0.9
0.9
0.9
1.0
1.0
Max
Min
65
75
Max
Min
70
80
Max
120K
45
20
20
15
15
1
1
120K
48
20
20
15
15
1
1
120K
ns
ns
ns
ns
ns
tCK
tCK
12
12
0.55
0.55
+0.75
+0.75
0.5
1.1
0.6
1.25
10
7.5
0.45
0.45
-0.75
-0.75
-
0.9
0.4
0.75
0
0.25
0.2
0.2
0.35
0.35
12
12
0.55
0.55
+0.75
+0.75
0.5
1.1
0.6
1.25
10
0.45
0.45
-0.8
-0.8
-
0.9
0.4
0.75
0
0.25
0.2
0.2
0.35
0.35
12
0.55
0.55
+0.8
+0.8
0.6
1.1
0.6
1.25
ns
ns
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
tCK
3
12
1.1
0.9
0.9
0.9
1.0
1.0
1.1
0.9
1.1
1.1
1.1
1.1
1.1
tCK
ns
ns
ns
ns
i,5.7
i,5.7
i,
i,
1
1
j, k
j, k
8
8
+0.75
+0.75
-0.75
15
0.5
0.5
2.2
1.75
7.5
75
200
+0.75
+0.75
-0.8
-0.8
16
0.6
0.6
2.5
2
10
80
200
+0.8
+0.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
us
7.8
1.5
15.6
0.67
1.5
4
Rev. 1.1 May. 2004