DDR SDRAM 128Mb F-die (x4, x8)
Block Diagram (8Mbit x 4
/
4Mbit x 8 I/O x 4 Banks)
DDR SDRAM
4/8
(L)WE
(L)DM
I/O Control
CK, CK
Data Input Register
Serial to parallel
Bank Select
8/16
4Mx8/ 2Mx16
Output Buffer
2-bit prefetch
Sense AMP
Refresh Counter
Row Buffer
Row Decoder
4Mx8/ 2Mx16
4Mx8/ 2Mx16
4Mx8/ 2Mx16
8/16
4/8
x4/x8
DQi
Address Register
CK, CK
ADD
Column Decoder
LCBR
LRAS
Col. Buffer
Latency & Burst Length
Strobe
Gen.
DLL
Data Strobe
Programming Register
LCKE
LRAS LCBR
LWE
LCAS
LWCBR
CK, CK
(L)DM
Timing Register
CK, CK
CKE
CS
RAS
CAS
WE
L(U)DM
Rev. 1.1 May. 2004