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K4H280838F-TC/LB3 Datasheet

  • K4H280838F-TC/LB3

  • 128Mb F-die DDR SDRAM Specification

  • 23頁

  • SAMSUNG   SAMSUNG

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DDR SDRAM 128Mb F-die (x4, x8)
Key Features
鈥?Double-data-rate architecture; two data transfers per clock cycle
鈥?Bidirectional data strobe(DQS)
鈥?Four banks operation
鈥?Differential clock inputs(CK and CK)
鈥?DLL aligns DQ and DQS transition with CK transition
鈥?MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
鈥?All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
鈥?Data I/O transactions on both edges of data strobe
鈥?Edge aligned data output, center aligned data input
鈥?DM for write masking only (x4, x8)
鈥?Auto & Self refresh
鈥?15.6us refresh interval(4K/64ms refresh)
鈥?Maximum burst refresh cycle : 8
鈥?66pin TSOP II package
DDR SDRAM
Ordering Information
Part No.
K4H280438F-TC/LA2
K4H280438F-TC/LB0
K4H280438F-TC/LA0
K4H280838F-TC/LB3
K4H280838F-TC/LA2
K4H280838F-TC/LB0
16M x 8
32M x 4
Org.
Max Freq.
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
A0(DDR200@CL=2)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
SSTL2
66pin TSOP II
SSTL2
66pin TSOP II
Interface
Package
Operating Frequencies
B3(DDR333@CL=2.5)
Speed @CL2
Speed @CL2.5
*CL : CAS Latency
133MHz
166MHz
A2(DDR266@CL=2.0)
133MHz
133MHz
B0(DDR266@CL=2.5)
100MHz
133MHz
A0(DDR200@CL=2.0)
100MHz
-
Rev. 1.1 May. 2004

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