DDR SDRAM 256Mb E-die (x4, x8)
B3
AA
(DDR333@CL=2.5)) (DDR266@CL=2.0)
Min
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
Control & Address input pulse width
DQ & DM input pulse width
Power down exit time
Exit self refresh to non-Read command
Exit self refresh to read command
Refresh interval time
Output DQS valid window
Clock half period
Data hold skew factor
DQS write postamble time
Active to Read with Auto precharge
command
Autoprecharge write recovery +
Precharge time
tMRD
tDS
tDH
tIPW
tDIPW
tPDEX
tXSNR
tXSRD
tREFI
tQH
tHP
tQHS
tWPST
tRAP
0.4
18
(tWR/tCK)
+
(tRP/tCK)
tHP
-tQHS
tCLmin
or tCHmin
12
0.45
0.45
2.2
1.75
6
75
200
7.8
-
-
0.55
0.6
0.4
20
(tWR/tCK)
+
(tRP/tCK)
tHP
-tQHS
tCLmin
or tCHmin
DDR SDRAM
A2
(DDR266@CL=2.0)
Min
15
0.5
0.5
2.2
1.75
7.5
75
200
7.8
-
-
0.75
0.6
0.4
20
(tWR/tCK)
+
(tRP/tCK)
tHP
-tQHS
tCLmin
or tCHmin
7.8
-
-
0.75
0.6
0.4
20
(tWR/tCK)
+
(tRP/tCK)
tHP
-tQHS
tCLmin
or tCHmin
Parameter
Symbol
B0
(DDR266@CL=2.5))
Min
15
0.5
0.5
2.2
1.75
7.5
75
200
7.8
-
-
0.75
0.6
Unit
ns
ns
ns
ns
ns
ns
ns
tCK
us
ns
ns
ns
tCK
Note
Max
Min
15
0.5
0.5
2.2
1.75
7.5
75
200
Max
Max
Max
j, k
j, k
8
8
4
11
10, 11
11
2
tDAL
tCK
13
Rev. 1.3 April. 2005