鈭?.1 V鈥?/div>
< 1 ns
275
10 < t
1
< 500
ms
DUTY CYCLE = 2%
t
1
+3 V
+10.9 V
275
10 k
1N916
C
S
< 4 pF*
0
* Total shunt capacitance of test jig and connectors
Figure 1. Delay and Rise Time
Equivalent Test Circuit
Figure 2. Storage and Fall Time
Equivalent Test Circuit
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