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L033MU11VI Datasheet

  • L033MU11VI

  • 32 Megabit (4 M x 8-Bit) MirrorBit⑩ 3.0 Volt-only Uniform S...

  • 1176.51KB

  • 61頁(yè)

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D A T A
S H E E T
Command Definitions
Table 10.
Cycles
First
Addr
RA
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
SA
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
55
Data
RD
F0
AA
AA
AA
AA
AA
AA
AA
AA
29
AA
AA
A0
90
AA
AA
B0
30
98
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A21鈥揂16 uniquely select any sector.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
WC = Byte Count. Number of write buffer locations to load minus 1.
XXX
XXX
PA
XXX
XXX
XXX
55
55
PD
00
55
55
XXX
XXX
80
80
XXX
XXX
AA
AA
XXX
XXX
55
55
XXX
SA
10
30
XXX
XXX
F0
20
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
55
55
55
55
55
55
55
55
XXX
XXX
XXX
XXX
XXX
XXX
XXX
SA
90
90
90
90
88
90
A0
25
XXX
PA
SA
00
PD
WC
PA
PD
WBL
PD
X00
X01
X03
(SA)X02
01
7E
(Note 9)
00/01
X0E
1C
X0F
00
Command Definitions
Bus Cycles (Notes 1鈥?)
Second
Third
Addr
Data
Fourth
Addr
Data
Fifth
Addr
Data
Sixth
Addr
Data
Command Sequence (Notes)
Read (Note 5)
Reset (Note 6)
Autoselect (Note 7)
Manufacturer ID
Device ID (Note 8)
SecSi鈩?Sector Factory Protect
(Note 9)
Sector Group Protect Verify
(Note 10)
Addr
Data
1
1
4
6
4
4
3
4
4
6
1
3
3
2
2
6
6
1
1
1
Enter SecSi Sector Region
Exit SecSi Sector Region
Program
Write to Buffer
Program Buffer to Flash
Write to Buffer Abort Reset (Note 11)
Unlock Bypass
Unlock Bypass Program (Note 12)
Unlock Bypass Reset (Note 13)
Chip Erase
Sector Erase
Program/Erase Suspend (Note 14)
Program/Erase Resume (Note 15)
CFI Query (Note 16)
Legend:
X = Don鈥檛 care
RA = Read Address of the memory location to be read.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on the falling edge of the WE#
or CE# pulse, whichever happens later.
PD = Program Data for location PA. Data latches on the rising edge of
WE# or CE# pulse, whichever happens first.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3.
4.
5.
6.
Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
During unlock and command cycles, when lower address bits are
don鈥檛 cares, address bits A21鈥揂12 are also don鈥檛 cares.
No unlock or command cycles required when device is in read
mode.
The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when the device is in the autoselect mode, or if DQ5 goes high
(while the device is providing status information).
The fourth cycle of the autoselect command sequence is a read
cycle. See the
Autoselect Command Sequence
section for more
information.
The device ID must be read in three cycles.
9.
The data is 88h for factory locked and 08h for not factory locked.
10. The data is 00h for an unprotected sector group and 01h for a
protected sector group.
11. Command sequence resets device for next command after
aborted write-to-buffer operation.
12. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
13. The Unlock Bypass Reset command is required to return to the
read mode when the device is in the unlock bypass mode.
14. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
15. The Erase Resume command is valid only during the Erase
Suspend mode.
16. Command is valid when device is ready to read array data or when
device is in autoselect mode.
7.
8.
32
Am29LV033MU
September 12, 2006

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