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P10C68-35IGDCBS Datasheet

  • P10C68-35IGDCBS

  • CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATI...

  • 17頁

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P10C68/P11C68
V
CC
5.0V
3.3V
t
AUTO RECALL
STORE INHIBIT
Figure 8. Automatic RECALL and STORE inhibit.
NON-VOLATILE MEMORY OPERATION OF P10C68
MODE SELECTION
E
H
L
L
L
L
L
L
W
X
H
L
H
L
L
H
G
X
L
X
L
H
L
H
NE
X
H
H
L
L
L
X
Not selected
Read RAM
Write RAM
Non-volatile recall (Note 15)
Non-volatile store
No operation
Mode
Power
Standby
Active
Active
Active
I
CC2
Active
NOTE
15.
An automatic RECALL also takes place on chip power-up, starting when Vcc exceeds 3.3V, and taking t
RECALL
from the
time at which Vcc exceeds 3.3V. Vcc must not drop below 3.3V once it has exceeded it for the RECALL to function
properly.
STORE CYCLE 1 : W (BAR) CONTROLLED
(See note 16)
Symbol
Standard
t
WLQX
t
GHNL
t
NLWL
t
WLNH
t
ELWL
Alternative
t
STORE
t
WC
Store cycle time
Output disable set-up to NE (bar) fall
Non-volatile set-up to write low
Write low to NE (bar) rise
Chip enable SET-UP
Parameter
P10C68-35
Min.
Max.
10
0
0
45
0
0
0
45
0
P10C68-45
Min.
Max.
10
ms
ns
ns
ns
ns
17
Units
Notes
18
8

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