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P10C68-35IGDCBS Datasheet

  • P10C68-35IGDCBS

  • CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATI...

  • 17頁(yè)

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P10C68/P11C68
t
AVAV
ADDRESS
t
ELQV
E
t
ELQX
t
EHQZ
G
DQ (DATA OUT)
ACTIVE
I
CC
STANDBY
t
ELICCH
t
GLQV
t
GHQZ
DATA VALID
t
EHICCL
t
GLQX
W
t
WHQV
F
igure 5. READ CYCLE 2 timing diagram (see note 9).
WRITE CYCLE 1 : W (BAR) CONTROLLED
(See notes 8 and 13)
Commercial and Industrial Temperature Range
Symbol
Standard
t
AVAV
t
WLWH
t
ELWH
t
DVWH
t
WHDX
t
AVWH
t
AVWL
t
WHAX
t
WLQZ
t
WHQZ
Alternative
t
WC
t
WP
t
CW
t
DW
t
DH
t
AW
t
AS
t
WR
t
WZ
t
OW
Write cycle time
Write pulse width
Chip enable to end of write
Data set-up to end of write
Data hold after end of write
Address set-up to end of write
Address set-up to start of write
Address hold after end of write
Write enable to output disable
Output active after end of write
Parameter
P10C68-35
P11C68-35
Max.
Min.
45
35
35
30
0
35
0
0
35
5
5
P10C68-45
P11C68-45
Max.
Min.
45
35
35
30
0
35
0
0
35
Units
Notes
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11, 14
NOTES
13.
E (bar) or W (bar) must be
鈮?/div>
VIH during address transitions.
14.
If W (bar) is low when E (bar) goes low, the outputs remain in the high impedance state.
6

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