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K4C89323AF-TCFB Datasheet

  • K4C89323AF-TCFB

  • 2,097,152-WORDS x 4 BANKS x 36-BITS DOUBLE DATA RATE Network...

  • 58頁

  • SAMSUNG   SAMSUNG

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K4C89363AF
Command Functions and Operations
K4C89363AF is introduced the two consecutive command input method. Therefore, except for Power Down mode, each operation
mode decided by the combination of the first command and the second command from stand-by states of the bank to be accessed.
Read Operation (1st command + 2nd command = RDA + LAL)
Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in
a read mode. When the LAL command with Lower Addresses is issued at the next clock of the RDA command, the data is read out
sequentially synchronizing with the both edges of QS output signal (Burst Read Operation). The initial valid read data appears a fter
C A S latency, the burst length of read data and the burst type must be set in the Mode Register beforehand. The read operated bank
g o e s b a c k a u t o m a t i c a l l y t o t h e i d l e s t a t e a f t e r I
RC
.
Write Operation (1st command + 2nd command = WRA + LAL)
Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in
a write mode. When the LAL command with Lower Addresses is issued at the next clock of the WRA command, the input data is
latched sequentially synchronizing with the both edges of DS input signal (Burst Write Operation). The data and DS inputs have to be
asserted in keeping with clock input after C A S latency-1 from the issuing of the LAL command. The DS have to be provided for a burst
length. The C A S latency and the burst type must be set in the Mode Register beforehand. The write operated bank goes back automat-
ically to the idle state after I
RC
. W r i t e B u r s t L e n g t h i s c o n t r o l l e d b y V W 0 a n d V W 1 i n p u t s w i t h L A L c o m m a n d . S e e V W t r u t h t a b l e .
Auto-Refresh Operation (1st command + 2nd command = WRA + REF)
K4C89363AF is required to refresh like a standard SDRAM. The Auto-Refresh operation is begun with the REF command following to
the WRA command. The Auto-Refresh mode can be effective only when all banks are in the idle state and all DQ are in Hi-Z states. In
a point to notice, the write mode started with the WRA command is canceled by the REF command having gone into the next clock of
the WRA command instead of the LAL command. The minimum period between the Auto-Refresh command and the next command is
specified by I
REFC
. H o w e v e r , a b o u t a s y n t h e t i c a v e r a g e i n t e r v a l o f A u t o - R e f r e s h c o m m a n d , i t m u s t b e c a r e f u l . I n c a s e o f e q u a l l y d i s -
tributed refresh, Auto-Refresh command has to be issued within once for every 3.9 us by the maximum In case of burst refresh or ran-
dom distributed refresh, the average interval of eight consecutive Auto-Refresh command has to be more than 400ns always. In oth er
words, the number of Auto-Refresh cycles which can be performed within 3.2 us (8x400ns) is to 8 times in the maximum.
Self-Refresh Operation (1st command + 2nd command = WRA + REF with PD ="L")
It is the function of Self-Refresh operation that refresh operation can be performed automatically by using an internal timer. When all
banks are in the idle state and all outputs are in Hi-z states, the K4C89363AF become Self-Refresh mode by issuing the Self-Refresh
c o m m a n d . P D h a s t o b e b r o u g h t t o " L o w " w i t h i n t
FPDL
f r o m t h e R E F c o m m a n d f o l l o w i n g t o t h e W R A c o m m a n d f o r a S e l f - R e f r e s h m o d e
entry. In order to satisfy the refresh period, the Self-Refresh entry command should be asserted within 3.9us after the latest Auto-
R e f r e s h c o m m a n d . O n c e t h e d e v i c e e n t e r s S e l f - R e f r e s h m o d e , t h e D E S L c o m m a n d m u s t b e c o n t i n u e d f o r I
REFC
period. In addition, it
is desirable that clock input is kept in I
CKD
period. The device is in Self-Refresh mode as long as P D held "Low". During Self-Refresh
mode, all input and output buffers except for PD are disabled, therefore the power dissipation lowers. Regarding a Self-Refresh mode
exit, P D h a s t o b e c h a n g e d o v e r f r o m " L o w " t o " H i g h " a l o n g w i t h t h e D E S L c o m m a n d , a n d t h e D E S L c o m m a n d h a s t o b e c o n t i n u o u s l y
i s s u e d i n t h e n u m b e r o f c l o c k s s p e c i f i e d b y I
REFC
. The Self-Refresh exit function is asynchronous operation. It is required that one
A u t o - R e f r e s h c o m m a n d i s i s s u e d t o a v o i d t h e v i o l e n c e o f t h e r e f r e s h p e r i o d j u s t a f t e r I
REFC
from Self-Refresh exit.
- 52 -
REV. 0.0 Nov. 2002

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