K4C89363AF
Mode Register Set Timing (CL=4, BL=4)
From Write operation to Mode Register Set operation
0
CLK
CLK
l
R C
=7cycles
WRA
LAL
DESL
RDA
MRS
DESL
RDA
or
WRA
LAL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Command
A14~A0
UA
LA
Valid
(opcode)
UA
LA
BA0, BA1
BA
WL + BL/2
BA0="0"
BA1="0"
BA
Unidirectional DS/QS mode
LDS/UDS
(Input)
LQS/UQS
(Output)
Low
DQ
(Output)
D0
D1
D2
D3
Unidirectional DS/Free Running QS mode
LDS/UDS
(Input)
LQS/UQS
(Output)
DQ
(Output)
D0
D1
D2
D3
Note : Minimum delay from LAL following WRA to RDA of MRS operation is WL+BL/2.
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REV. 0.0 Sep. 2002