K4C89363AF
Multiple Bank Write Timing (CL=4)
0
CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
l
R B D
=2cycles
WRA
LAL
WRA
LAL
DESL
WRA
l
R B D
= 2 c y c l e s
LAL
WRA
l
R B D
= 2 c y c l e s
LAL
WRA
l
R B D
= 2 c y c l e s
LAL
WRA
l
R B D
= 2 c y c l e s
LAL
WRA
LAL
WRA
Command
Address
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank Add.
Bank
"a"
Bank
"b"
l
RC
(Bank"a")=5cycles
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
l
R C
(Bank"b")=5cycles
Unidirectional DS/QS mode
BL =2
LDS/UDS
(Input)
Low
LQS/UQS
(Output)
WL=3
DQ
(Output)
WL=3
D a 0 Da1
D b 0 Db1
Da0 Da1
Db0 Db1
Dc0 Dc1
Dd0 Dd1
BL =4
LDS/UDS
(Input)
Low
LQS/UQS
(Output)
WL=3
DQ
(Output)
Unidirectional DS/Free Running QS mode
BL =2
LDS/UDS
(Input)
WL=3
D a 0 Da1 D a 2 D a 3 Db0 D b 1 Db2 D b 3
D a 0 D a 1 D a 2 Da3 D b 0 Db1 D b 2 Db3 Dc0 Dc1 Dc2 Dc3 D d 0 D d 1
LQS/UQS
(Output)
WL=3
DQ
(Output)
WL=3
D a 0 Da1
D b 0 Db1
Da0 Da1
Db0 Db1
Dc0 Dc1
Dd0 Dd1
BL =4
LDS/UDS
(Input)
LQS/UQS
(Output)
WL=3
DQ
(Output)
WL=3
D a 0 Da1 D a 2 D a 3 Db0 D b 1 Db2 D b 3
D a 0 D a 1 D a 2 Da3 D b 0 Db1 D b 2 Db3 Dc0 Dc1 Dc2 Dc3 D d 0 D d 1
- 35 -
REV. 0.0 Sep. 2002