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K4C89323AF-TCFB Datasheet

  • K4C89323AF-TCFB

  • 2,097,152-WORDS x 4 BANKS x 36-BITS DOUBLE DATA RATE Network...

  • 58頁

  • SAMSUNG   SAMSUNG

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K4C89363AF
2,097,152-WORDS x 4 BANKS x 36-BITS DOUBLE DATA RATE Network-DRAM
DESCRIPTION
K4C89363AF is a CMOS Double Data Rate Network-DRAM containing 301,989,888 memory cells. K4C89363AF is organized as
2,097,152-words x 4 banks x36 bits. K4C89363AF feature a fully synchronous operation referenced to clock edge whereby all opera-
tions are synchronized at a clock input which enables high performance and simple user interface coexistence. K4C89363AD can
operate fast core cycle compared with regular DDR SDRAM.
K4C89363AF is suitable for Server, Network and other applications where large memory density and low power consumption are
required. The Output Driver for Network-DRAM is capable of high quality fast data transfer under light loading condition.
FEATURES
K4C89363AF
Parameter
F6
CL = 4
t
C K
C l o c k C y c l e T i m e ( m i n )
CL = 5
CL = 6
t
RC
R a n d o m R e a d / W r i t e C y c l e T i m e ( m i n )
t
R A C
R a n d o m A c c e s s T i m e ( m i n )
I
D D 1 S
O p e r a t i n g C u r r e n t ( s i n g l e b a n k ) ( m a x )
I
D D 2 S
P o w e r D o w n C u r r e n t ( m a x )
I
D D 3 S
S e l f - R e f r e s h C u r r e n t ( m a x )
鈥?/div>
Fully Synchronous Operation
- Double Data Rate (DDR)
- Data input/output are synchronized with both edges of DS / QS.
- Differential Clock (CLK and C L K ) inputs
- C S, FN and all address input signals are sampled on the positive edge of CLK.
- Output data (DQs and QS) is aligned to the crossings of CLK and CLK.
鈥?/div>
Fast clock cycle time of 3.0 ns minimum
- Clock : 333 MHz maximum
- Data : 666 Mbps/pin maximum
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Quad Independent Banks operation
Fast cycle and Short Latency
Selectable Data Strobe(Uni/Bi-directional data strobe)
Distributed Auto-Refresh cycle in 3.9us
Self-Refresh
Power Down Mode
Variable Write Length Control
Write Latency = C A S Latency-1
Programable C A S Latency and Burst Length
- C A S Laatency = 4, 5, 6
- Burst Length = 2,4
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Organization : 2,097,152 words x 4 banks x 36 bits
P o w e r S u p p l y V o l t a g e V
DD
: 2 . 5 V
鹵
0 . 1 2 5 V
V
DDQ
: 1 . 8 V
鹵
0 . 1 V
1.8V CMOS I/O comply with SSTL - 1.8 (half strength driver)
Package : 144Ball BGA, 1mm x 0.8mm Ball pitch
JTAG(for x36)
Notice : Network-DRAM is trademark of Samsung Electronics., Co LTD
4.0 ns
3.33 ns
3.0ns
20.0 ns
20.0 ns
TBD
TBD
TBD
FB
4.5 ns
3.75 ns
3.33 ns
22.5 ns
22.5 ns
TBD
TBD
TBD
F5
5.0 ns
4.5 ns
4.0 ns
25 ns
25 ns
TBD
TBD
TBD
- 3 -
REV. 0.0 Nov. 2002

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