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ESMT

Register Programmed with MRS

Address

Function

BA

RFU

A11~A10/AP

RFU

A9

Preliminary

M12L32162A

MODE REGISTER FIELD TABLE TO PROGRAM MODES

A8

TM

A7

A6

A5

A4

A3

BT

A2

A1

A0

W.B.L

CAS Latency

Burst Length

Test Mode

A8

0

0

1

1

A7

0

1

0

1

Type

Mode Register Set

Reserved

Reserved

Reserved

A6

0

0

0

0

1

1

1

1

CAS Latency

A5

0

0

1

1

0

0

1

1

A4

0

1

0

1

0

1

0

1

Latency

Reserved

Reserved

2

3

Reserved

Reserved

Reserved

Reserved

Burst Type

A3

0

1

Type

Sequential

Interleave

A2

0

0

0

0

1

1

1

1

A1

0

0

1

1

0

0

1

1

Burst Length

A0

0

1

0

1

0

1

0

1

BT = 0

1

2

4

8

BT = 1

1

2

4

8

Write Burst Length

A9

0

1

Length

Burst

Single Bit

Reserved Reserved

Reserved Reserved

Reserved Reserved

Full Page Reserved

Full Page Length : 256

POWER UP SEQUENCE

1.Apply power and start clock, Attempt to maintain CKE = 鈥滺鈥? DQM = 鈥滺鈥?and the other pin are NOP condition at the inputs.

2. Maintain stable power , stable clock and NOP input condition for a minimum of 200us.

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue mode register set command to initialize the mode register.

cf.) Sequence of 4 & 5 is regardless of the order.

The device is now ready for normal operation.

Note :

1. RFU(Reserved for future use) should stay 鈥?鈥?during MRS cycle.

2. If A9 is high during MRS cycle, 鈥淏urst Read Single Bit Write鈥?function will be enabled.

3. The full column burst (256 bit) is available only at sequential mode of burst type.

Elite Semiconductor Memory Technology Inc.

Publication Date

:

Apr. 2007

Revision

:

0.3

8/29

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