最新免费av在线观看,亚洲综合一区成人在线,中文字幕精品无码一区二区三区,中文人妻av高清一区二区,中文字幕乱偷无码av先锋

M12L32162A-7BG Datasheet

  • M12L32162A-7BG

  • 1M x 16Bit x 2Banks Synchronous DRAM

  • 29頁

  • ESMT

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預覽

ESMT
Self Refresh Entry & Exit Cycle
0
CLOCK
*Note2
*Note1
Preliminary
2
3
4
5
6
7
8
9
10
11
12
13
14
M12L32162A
1
15
16
17
18
19
*Note4
t
RCmin
*Note6
CKE
*Note3
t
SS
CS
*Note5
RAS
*Note7
CAS
ADDR
BA
A10 /AP
DQ
Hi-Z
Hi-Z
WE
DQM
Sel f R ef r esh En tr y
S e l f R ef r e s h E xi t
Auto Refresh
: Don't care
*Note: TO ENTER SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don鈥檛 care except for CKE.
3. The device remains in self refresh mode as long as CKE stays 鈥淟ow鈥?
cf.) Once the device enters self refresh mode, minimum t
RAS
is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS Starts from high.
6. Minimum t
RC
is required after CKE going high to complete self refresh exit.
7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst
refresh.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Apr. 2007
Revision
:
0.3
25/29

M12L32162A-7BG相關型號PDF文件下載

您可能感興趣的PDF文件資料

熱門IC型號推薦

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務：
賣家服務：
技術客服：

0571-85317607

網(wǎng)站技術支持

13606545031

客服在線時間周一至周五
9:00-17:30

關注官方微信號，
第一時間獲取資訊。

建議反饋
返回頂部

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！