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ESMT

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Preliminary

M12L32162A

Page Read Cycle at Different Bank @ Burst Length=4

7

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16

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CLOCK

CKE

*Note1

HIGH

CS

RAS

*Note2

CAS

ADDR

RAa

CAa

RBb

CBb

CAc

CBd

CAe

BA

A10/AP

RAa

RBb

CL=2

DQ

CL=3

QAa0

QAa1

QAa2

QAa3

QBb0

QBb1

QBb2

QBb3

QAc0

QAc1

QBd0

QBd1

QAe0

QAe1

QAa0

QAa1

QAa2

QAa3

QBb0

QBb1

QBb2 QBb3

QAc0

QAc1

QBd0

QBd1

QAe0

QAe1

WE

DQM

Row Active

(A-Bank)

Read

(A-Bank)

Row Active

(B-Bank)

Read

(B-Bank)

Read

(A-Bank)

Read

(B-Bank)

Read

(A-Bank)

Precharge

(A-Bank)

: Don't care

*Note: 1. CS can be don鈥檛 cared when RAS , CAS and

WE

are high at the clock high going dege.

2.To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.

Elite Semiconductor Memory Technology Inc.

Publication Date

:

Apr. 2007

Revision

:

0.3

16/29

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