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M12L32162A-7BG Datasheet

  • M12L32162A-7BG

  • 1M x 16Bit x 2Banks Synchronous DRAM

  • 29頁(yè)

  • ESMT

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ESMT
SIMPLIFIED TRUTH TABLE
COMMAND
Register
Refresh
Mode Register Set
Auto Refresh
Entry
Self Refresh
Exit
Preliminary
M12L32162A
CKEn-1 CKEn CS
H
H
L
H
H
H
H
X
H
L
H
X
X
X
X
X
L
H
L
H
X
L
L
L
H
L
L
L
L
L
H
L
X
H
L
H
L
H
L
RAS
L
L
H
X
L
H
H
H
L
X
V
X
X
H
X
V
X
X
H
CAS
L
L
H
X
H
L
L
H
H
X
V
X
X
H
X
V
X
H
WE
DQM BA A10/AP
X
X
X
X
X
X
X
X
X
X
X
X
V
X
X
X
X
V
X
L
H
X
V
V
V
L
H
H
X
H
H
L
L
L
X
V
X
X
H
X
V
X
H
A11
Note
A9~A0
OP CODE
1,2
3
X
3
X
Row Address
Column
L
H
L
H
X
X
3
3
4
Address
(A0~A7)
4,5
Column
4
Address
4,5
(A0~A7)
Bank Active & Row Addr.
Auto Precharge Disable
Read &
Column Address
Write & Column
Address
Burst Stop
Precharge
Clock Suspend or
Active Power Down
Precharge Power Down Mode
DQM
No Operation Command
Bank Selection
Both Banks
Entry
Exit
Entry
Exit
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
H
H
L
H
L
H
H
H
6
4
4
7
(V= Valid, X= Don鈥檛 Care, H= Logic High , L = Logic Low)
Note:
1. OP Code: Operation Code
A0~ A11, BA: Program keys.(@MRS)
2.
3.
MRS can be issued only at both banks precharge state.
A new command can be issued after 2 clock cycle of MRS.
Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by 鈥淎uto鈥?
Auto / self refresh can be issued only at both banks idle state.
4.
BA: Bank select address.
If 鈥淟ow鈥? at read, write, row active and precharge, bank A is selected.
If 鈥淗igh鈥? at read, write, row active and precharge, bank B is selected.
If A10/AP is 鈥淗igh鈥?at row precharge, BA ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read /write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
RP
after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but
makes
Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Apr. 2007
Revision
:
0.3
10/29

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