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M12L128324A-7TG Datasheet

  • M12L128324A-7TG

  • 1M x 32 Bit x 4 Banks Synchronous DRAM

  • 47頁

  • ESMT

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ESMT
Self Refresh Entry & Exit Cycle
0
CLOCK
*Note2
*Note1
*Note4
M12L128324A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
t
RCmin
*Note6
CKE
*Note3
t
SS
CS
*Note5
RAS
*Note7
CAS
ADDR
BA0, BA1
A10 /A P
DQ
Hi-Z
Hi-Z
WE
DQM
Self Ref r esh En tr y
S e l f R ef r e s h E xi t
Auto Ref res h
: Don't care
*Note :
TO ENTER SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don鈥檛 care except for CKE.
3. The device remains in self refresh mode as long as CKE stays 鈥淟ow鈥?
cf.) Once the device enters self refresh mode, minimum t
RAS
is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum t
RC
is required after CKE going high to complete self refresh exit.
7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst
refresh.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2006
Revision: 1.2
43/47

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