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M12L128324A-7TG Datasheet

  • M12L128324A-7TG

  • 1M x 32 Bit x 4 Banks Synchronous DRAM

  • 47頁(yè)

  • ESMT

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ESMT
COMMANDS
Mode register set command
( CS , RAS , CAS ,
WE
= Low)
The M12L128324A has a mode register that defines how the device operates. In
this command, A0 through A10 and BA0~BA1 are the data input pins. After power on,
the mode register set command must be executed to initialize the device.
The mode register can be set only when all banks are in idle state.
During 2CLK following this command, the M12L128324A cannot accept any
other commands.
M12L128324A
CLK
CKE
CS
RAS
CAS
WE
BA0, BA1
(Bank select)
H
A10
Add
Fig. 1 Mode register set
command
Activate command
( CS , RAS = Low, CAS ,
WE
= High)
The M12L128324A has four banks, each with 2,048 rows.
This command activates the bank selected by BA1 and BA0 and a row address
selected by A0 through A10.
This command corresponds to a conventional DRAM鈥檚 RAS falling.
CLK
CKE
CS
RAS
CAS
WE
BA0, BA1
(Bank select)
H
A10
Add
Row
Row
Fig. 2 Row address stroble and
bank active command
Precharge command
( CS , RAS ,
WE
= Low, CAS = High )
This command begins precharge operation of the bank selected by BA1 and BA0.
When A10 is High, all banks are precharged, regardless of BA1 and BA0. When A10
is Low, only the bank selected by BA1 and BA0 is precharged.
After this command, the M12L128324A can鈥檛 accept the activate command to the
precharging bank during t
RP
(precharge to activate command period).
This command corresponds to a conventional DRAM鈥檚 RAS rising.
CLK
CKE
CS
RAS
CAS
WE
(Bank select)
(Precharge select)
H
BA0, BA1
A10
Add
Fig. 3 Precharge command
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2006
Revision: 1.2
16/47

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