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M12L128324A-7TG Datasheet

  • M12L128324A-7TG

  • 1M x 32 Bit x 4 Banks Synchronous DRAM

  • 47頁

  • ESMT

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ESMT
SIMPLIFIED TRUTH TABLE
COMMAND
Register
Mode Register set
Auto Refresh
Refresh
Self
Refresh
Entry
Exit
CKEn-1
H
H
CKEn
X
H
L
H
X
X
CS RAS CAS
L
L
L
H
L
L
L
L
H
X
L
H
L
L
H
X
H
L
WE
M12L128324A
DQM BA0,1 A10/AP
X
X
X
X
X
X
V
V
OP CODE
X
A9~A0
Note
1,2
3
3
3
3
L
H
H
X
H
H
L
H
H
X
Row Address
L
H
L
H
X
V
X
L
H
X
Column
Address
(A0~A7)
Column
Address
(A0~A7)
Bank Active & Row Addr.
Read &
Column Address
Write &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
4
4,5
4
4,5
6
H
H
H
X
X
X
L
L
L
H
L
X
H
L
H
L
H
H
L
X
V
X
X
H
X
V
X
L
H
H
X
V
X
X
H
X
V
L
L
L
X
V
X
X
H
X
V
X
X
X
V
Burst Stop
Precharge
Bank Selection
All Banks
Clock Suspend or
Active Power Down
Entry
Exit
Entry
Precharge Power Down Mode
Exit
DQM
No Operating Command
H
L
H
L
H
L
X
X
X
X
X
X
V
X
X
7
L
H
H
H
X
H
L
X
H
X
H
X
H
X
(V = Valid , X = Don鈥檛 Care. H = Logic High , L = Logic Low )
Note :
1.OP Code : Operating Code
A0~A11 & BA0~BA1 : Program keys. (@ MRS)
2.MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3.Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge of command is meant by 鈥淎uto鈥?
Auto/self refresh can be issued only at all banks idle state.
4.BA0~BA1 : Bank select addresses.
If both BA1 and BA0 are 鈥淟ow鈥?at read ,write , row active and precharge ,bank A is selected.
If both BA1 is 鈥淟ow鈥?and BA0 is 鈥淗igh鈥?at read ,write , row active and precharge ,bank B is selected.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2006
Revision: 1.2
10/47

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