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M12S64322A-6BG Datasheet

  • M12S64322A-6BG

  • 512K x 32 Bit x 4 Banks Synchronous DRAM

  • 46頁

  • ESMT

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ESMT
Version
Parameter
Col. address to col. address delay
Number of valid
Output data
Symbol
-6
t
CCD(min)
1
2
1
-7
CLK
ea
Unit
M12S64322A
Note
3
4
CAS latency = 3
CAS latency = 2
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
AC CHARACTERISTICS
(AC operating condition unless otherwise noted)
-6
Parameter
Symbol
Min
CLK cycle time
CLK to valid
output delay
Output data
hold time
CLK high pulsh width
CLK low pulsh width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output
in Hi-Z
Note :
CAS latency = 3
CAS latency = 2
CAS latency = 3
CAS latency = 2
CAS latency = 3
CAS latency = 2
CAS latency = 3
CAS latency = 2
t
CH
t
CL
t
SS
t
SH
t
SLZ
t
SHZ
t
OH
2
2
2.5
2.5
1.5
1
1
5.5
6
t
SAC
t
CC
6
10
5.5
6
2
2
2.5
2.5
2
1
1
6
6
ns
ns
ns
ns
ns
ns
3
3
3
3
2
Max
1000
Min
7
10
6
6
ns
2
ns
1,2
Max
1000
ns
1
-7
Unit
Note
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered.
3. Assumed input rise and fall time (tr & tf) =1ns.
If tr & tf is longer than 1ns. transient time compensation should be considered.
i.e., [(tr + tf)/2 鈥?1] ns should be added to the parameter.
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision: 1.0
8/46

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