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M12S64322A-6BG Datasheet

  • M12S64322A-6BG

  • 512K x 32 Bit x 4 Banks Synchronous DRAM

  • 46頁(yè)

  • ESMT

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ESMT
FUNCTION TRUTH TABLE (TABLE2)
Current
State
CKE
( n-1 )
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
L
L
CKE
n
X
H
H
H
H
H
L
X
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
H
L
H
L
CS
RAS CAS
M12S64322A
WE
ADDR
ACTION
Note
Self
Refresh
All
Banks
Precharge
Power
Down
All
Banks
Idle
Any State
other than
Listed
above
X
H
L
L
L
L
X
X
H
L
L
L
L
X
X
H
L
L
L
L
L
L
X
X
X
X
X
X
X
H
H
H
L
X
X
X
H
H
H
L
X
X
X
H
H
H
L
L
L
X
X
X
X
X
X
X
H
H
L
X
X
X
X
H
H
L
X
X
X
X
H
H
L
H
L
L
X
X
X
X
X
X
X
H
L
X
X
X
X
X
H
L
X
X
X
X
X
H
L
X
H
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RA
X
OP Code
X
X
X
X
X
INVALID
Exit Self Refresh
Idle after t
RC
(ABI)
Exit Self Refresh
Idle after t
RC
(ABI)
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Self Refresh)
INVALID
Exit Self Refresh
ABI
Exit Self Refresh
ABI
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Low Power Mode)
Refer to Table1
Enter Power Down
Enter Power Down
ILLEGAL
ILLEGAL
Row (& Bank) Active
Enter Self Refresh
Mode Register Access
NOP
Refer to Operations in Table 1
Begin Clock Suspend next cycle
Exit Clock Suspend next cycle
Maintain Clock Suspend
6
6
7
7
8
8
8
9
9
Abbreviations
:
ABI = All Banks Idle, RA = Row Address
*Note : 6.CKE low to high transition is asynchronous.
7.CKE low to high transition is asynchronous if restart internal clock.
A minimum setup time 1CLK + t
SS
must be satisfy before any command other than exit.
8.Power down and self refresh can be entered only from the all banks idle state.
9.Must be a legal command.
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision: 1.0
28/46

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