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M12S64322A-6BG Datasheet

  • M12S64322A-6BG

  • 512K x 32 Bit x 4 Banks Synchronous DRAM

  • 46頁

  • ESMT

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ESMT
Current
State
CS
RAS
CAS
M12S64322A
WE
BA
ADDR
ACTION
Note
Precharging
Row
Activating
Refreshing
Mode
Register
Accessing
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
X
H
H
H
L
L
L
X
H
H
H
L
L
L
X
H
H
L
L
X
H
H
H
L
X
H
H
L
H
H
L
X
H
H
L
H
H
L
X
H
L
H
L
X
H
H
L
X
X
H
L
X
H
L
X
X
H
L
X
H
L
X
X
X
X
X
X
X
H
L
X
X
X
X
X
BA
BA
BA
X
X
X
X
BA
BA
BA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CA
RA
A10/AP
X
X
X
X
CA
RA
A10/AP
X
X
X
X
X
X
X
X
X
X
X
NOP
Idle after t
RP
NOP
Idle after t
RP
ILLEGAL
ILLEGAL
ILLEGAL
NOP
Idle after t
RDL
ILLEGAL
NOP
Row Active after t
RCD
NOP
Row Active after t
RCD
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP
Idle after t
RC
NOP
Idle after t
RC
ILLEGAL
ILLEGAL
ILLEGAL
NOP
Idle after 2clocks
NOP
Idle after 2clocks
ILLEGAL
ILLEGAL
ILLEGAL
BA = Bank Address
CA = Column Address
2
2
2
4
2
2
2
2
Abbreviations :
RA = Row Address
NOP = No Operation Command
AP = Auto Precharge
*Note : 1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle.
2. Illegal to bank in specified state ; Function may be legal in the bank indicated by BA, depending on the state of the
bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharge or in idle state. May precharge bank indicated by BA (and A10/AP).
5. Illegal if any bank is not idle.
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision: 1.0
27/46

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