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M12S64322A-6BG Datasheet

  • M12S64322A-6BG

  • 512K x 32 Bit x 4 Banks Synchronous DRAM

  • 725.62KB

  • 46頁(yè)

  • ESMT

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ESMT
10. Clock Suspend Exit & Power Down Exit
1) Cl o ck S u sp en d (= Ac t ive P ow er Do wn ) Exi t
M12S64322A
2)P ower Down (= Pr ec ha rg e Power Down )
CLK
CKE
CLK
CKE
t
SS
Inter nal
CLK
CMD
*Note1
t
SS
*Note2
Internal
CLK
RD
CMD
NOP AC T
11. Auto Refresh & Self Refresh
1)Auto Refresh &
Self Refresh
*Note3
CLK
*Note4
*Note5
CM D
PRE
AR
CM D
CKE
t
RP
2)Self R efresh
*Note8
t
RC
CLK
*Note4
CM D
PRE
SR
CM D
CKE
t
RP
t
RC
*Note
:
1. Active power down : one or more banks active state.
2. Precharge power down : all banks precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after auto refresh command.
During t
RC
from auto refresh command, any other command can not be accepted.
4. Before executing auto/self refresh command, all banks must be idle state.
5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh entry, refresh interval and refresh operation are performed internally.
After self refresh entry, self refresh mode is kept while CKE is low.
During self refresh entry, all inputs expect CKE will be don鈥檛 cared, and outputs will be in Hi-Z state.
For the time interval of t
RC
from self refresh exit command, any other command can not be accepted.
Before/After self refresh mode, burst auto refresh (40% cycles) is recommended.
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision: 1.0
24/46

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