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M12S64322A-6BG Datasheet

  • M12S64322A-6BG

  • 512K x 32 Bit x 4 Banks Synchronous DRAM

  • 725.62KB

  • 46頁(yè)

  • ESMT

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ESMT
Self refresh entry command
CLK
M12S64322A
( CS , RAS , CAS , CKE = Low ,
WE
= High)
After the command execution, self refresh operation continues while CKE
remains low. When CKE goes to high, the DRAM exits the self refresh mode.
During self refresh mode, refresh interval and refresh operation are performed
internally, so there is no need for external control.
Before executing self refresh, all banks must be precharged.
CKE
CS
RAS
CAS
WE
BA0, BA1
(Bank select)
A10
Add
Fig. 7 Self refresh entry
command
Burst stop command
( CS ,
WE
= Low, RAS , CAS = High)
This command terminates the current burst operation.
Burst stop is valid at every burst length.
CLK
CKE
CS
RAS
CAS
WE
BA0, BA1
(Bank select)
H
A10
Add
Fig. 8 Burst stop command
CLK
No operation
( CS = Low , RAS , CAS ,
WE
= High)
This command is not a execution command. No operations begin or terminate by
this command.
CKE
CS
RAS
CAS
WE
BA0, BA1
(Bank select)
H
A10
Add
Fig. 9 No operation
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision: 1.0
17/46

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